2006-02-22 04:02:05 +01:00
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/*
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2007-11-17 03:32:22 +01:00
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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2007-11-15 20:21:01 +01:00
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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2006-02-22 04:02:05 +01:00
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*
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2007-11-15 20:21:01 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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2006-02-22 04:02:05 +01:00
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*
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2007-11-15 20:21:01 +01:00
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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2007-11-15 20:21:01 +01:00
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* Authors: Gabe Black
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* Korey Sewell
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2007-11-13 22:58:16 +01:00
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* Jaidev Patwardhan
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2006-02-22 04:02:05 +01:00
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*/
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2006-03-08 08:05:38 +01:00
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#include "arch/mips/faults.hh"
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2007-11-13 22:58:16 +01:00
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#include "arch/mips/pra_constants.hh"
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2010-09-10 23:58:04 +02:00
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/MipsPRA.hh"
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2010-09-10 23:58:04 +02:00
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2006-06-26 22:49:05 +02:00
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#if !FULL_SYSTEM
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#include "mem/page_table.hh"
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2010-09-10 23:58:04 +02:00
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#include "sim/process.hh"
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2006-06-26 22:49:05 +02:00
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#endif
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2006-03-12 11:57:34 +01:00
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namespace MipsISA
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{
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2011-09-19 15:17:19 +02:00
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typedef MipsFaultBase::FaultVals FaultVals;
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<MachineCheckFault>::vals =
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{ "Machine Check", 0x0401 };
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<ResetFault>::vals =
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2007-11-13 22:58:16 +01:00
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#if FULL_SYSTEM
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2011-09-19 15:17:19 +02:00
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{ "Reset Fault", 0xBFC00000};
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2007-11-13 22:58:16 +01:00
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#else
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2011-09-19 15:17:19 +02:00
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{ "Reset Fault", 0x001};
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2007-11-13 22:58:16 +01:00
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#endif
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<AddressErrorFault>::vals =
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{ "Address Error", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<StoreAddressErrorFault>::vals =
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{ "Store Address Error", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<SystemCallFault>::vals =
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{ "Syscall", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
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{ "Coprocessor Unusable Fault", 0x180 };
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2007-06-23 01:03:42 +02:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
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{ "Reserved Instruction Fault", 0x0180 };
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2007-06-23 01:03:42 +02:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<ThreadFault>::vals =
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{ "Thread Fault", 0x00F1 };
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2007-06-23 01:03:42 +02:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
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{ "Integer Overflow Exception", 0x180 };
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2007-06-23 01:03:42 +02:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<InterruptFault>::vals =
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{ "interrupt", 0x0180 };
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<TrapFault>::vals =
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{ "Trap", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<BreakpointFault>::vals =
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{ "Breakpoint", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<ItbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<ItbRefillFault>::vals =
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{ "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
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2007-11-13 22:58:16 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<DtbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception (Store)", 0x0180 };
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<DtbRefillFault>::vals =
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{ "TLB Refill Exception (Store)", 0x0180 };
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<TLBModifiedFault>::vals =
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{ "TLB Modified Exception", 0x0180 };
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2006-03-12 11:57:34 +01:00
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2011-09-19 15:17:19 +02:00
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template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
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{ "DSP Disabled Fault", 0x001a };
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2007-06-23 01:03:42 +02:00
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2007-11-13 22:58:16 +01:00
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#if FULL_SYSTEM
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2009-07-21 10:08:53 +02:00
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void
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2011-09-19 15:17:19 +02:00
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MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
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2007-06-23 01:03:42 +02:00
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{
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2009-07-21 10:08:53 +02:00
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tc->setPC(HandlerBase);
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tc->setNextPC(HandlerBase + sizeof(MachInst));
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tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
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2007-06-23 01:03:42 +02:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2011-09-19 15:17:19 +02:00
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MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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// modify SRS Ctl - Save CSS, put ESS into CSS
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2009-07-22 08:38:26 +02:00
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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2009-07-21 10:09:05 +02:00
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if (status.exl != 1 && status.bev != 1) {
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2009-07-21 10:08:53 +02:00
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// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
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2009-07-22 08:38:26 +02:00
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SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
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2009-07-21 10:09:05 +02:00
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srsCtl.pss = srsCtl.css;
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srsCtl.css = srsCtl.ess;
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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// set EXL bit (don't care if it is already set!)
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2009-07-21 10:09:05 +02:00
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status.exl = 1;
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_STATUS, status);
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2009-07-21 10:08:53 +02:00
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// write EPC
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// CHECK ME or FIXME or FIX ME or POSSIBLE HACK
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// Check to see if the exception occurred in the branch delay slot
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DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
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tc->readPC(), tc->readNextPC(), tc->readNextNPC());
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2009-07-21 10:09:05 +02:00
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int bd = 0;
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2009-07-21 10:08:53 +02:00
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if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst));
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2009-07-21 10:08:53 +02:00
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// In the branch delay slot? set CAUSE_31
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2009-07-21 10:09:05 +02:00
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bd = 1;
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2009-07-21 10:08:53 +02:00
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} else {
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC());
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2009-07-21 10:08:53 +02:00
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// In the branch delay slot? reset CAUSE_31
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2009-07-21 10:09:05 +02:00
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bd = 0;
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2009-07-21 10:08:53 +02:00
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}
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2007-11-13 22:58:16 +01:00
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2009-07-21 10:08:53 +02:00
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// Set Cause_EXCCODE field
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2009-07-22 08:38:26 +02:00
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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2009-07-21 10:09:05 +02:00
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cause.excCode = excCode;
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cause.bd = bd;
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cause.ce = 0;
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2011-09-19 15:17:19 +02:00
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IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xC);
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// Set new PC
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Addr HandlerBase;
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2009-07-22 08:38:26 +02:00
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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2009-07-21 10:08:53 +02:00
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// Here, the handler is dependent on BEV, which is not modified by
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// setExceptionState()
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2009-07-21 10:09:05 +02:00
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if (!status.bev) {
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2009-07-21 10:08:53 +02:00
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// See MIPS ARM Vol 3, Revision 2, Page 38
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2009-07-22 08:38:26 +02:00
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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2009-07-21 10:08:53 +02:00
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} else {
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HandlerBase = 0xBFC00200;
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}
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setHandlerPC(HandlerBase, tc);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2010-09-14 04:26:03 +02:00
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StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x5);
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
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2007-11-13 22:58:16 +01:00
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2009-07-21 10:08:53 +02:00
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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2009-07-22 08:38:26 +02:00
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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2009-07-21 10:08:53 +02:00
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setHandlerPC(HandlerBase, tc);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2010-09-14 04:26:03 +02:00
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TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xD);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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2009-07-22 08:38:26 +02:00
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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2009-07-21 10:08:53 +02:00
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setHandlerPC(HandlerBase, tc);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2010-09-14 04:26:03 +02:00
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BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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setExceptionState(tc, 0x9);
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2007-11-13 22:58:16 +01:00
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2009-07-21 10:08:53 +02:00
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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2009-07-22 08:38:26 +02:00
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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2009-07-21 10:08:53 +02:00
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setHandlerPC(HandlerBase, tc);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2010-09-14 04:26:03 +02:00
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DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-06-23 01:03:42 +02:00
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{
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2009-07-21 10:08:53 +02:00
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
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EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
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2009-07-21 10:09:05 +02:00
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entryHi.asid = entryHiAsid;
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entryHi.vpn2 = entryHiVPN2;
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entryHi.vpn2x = entryHiVPN2X;
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
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2009-07-21 10:09:05 +02:00
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2009-07-22 08:38:26 +02:00
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ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
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2009-07-21 10:09:05 +02:00
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context.badVPN2 = contextBadVPN2;
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2009-07-22 08:38:26 +02:00
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tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
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2009-07-21 10:08:53 +02:00
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setExceptionState(tc, 0x3);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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2009-07-22 08:38:26 +02:00
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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2009-07-21 10:09:05 +02:00
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setHandlerPC(HandlerBase, tc);
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2007-11-13 22:58:16 +01:00
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}
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2009-07-21 10:08:53 +02:00
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void
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2010-09-14 04:26:03 +02:00
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AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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2007-11-13 22:58:16 +01:00
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{
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2009-07-21 10:08:53 +02:00
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DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0x4);
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
|
2009-07-21 10:08:53 +02:00
|
|
|
|
|
|
|
// Set new PC
|
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0x2);
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
|
|
|
|
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
|
2009-07-21 10:09:05 +02:00
|
|
|
entryHi.asid = entryHiAsid;
|
|
|
|
entryHi.vpn2 = entryHiVPN2;
|
|
|
|
entryHi.vpn2x = entryHiVPN2X;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
|
2009-07-21 10:09:05 +02:00
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
|
2009-07-21 10:09:05 +02:00
|
|
|
context.badVPN2 = contextBadVPN2;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
|
2009-07-21 10:08:53 +02:00
|
|
|
|
|
|
|
|
|
|
|
// Set new PC
|
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase,tc);
|
2009-07-21 10:09:05 +02:00
|
|
|
DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase, tc->readMiscReg(MISCREG_EPC));
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2009-07-22 08:38:26 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
|
2009-07-21 10:08:53 +02:00
|
|
|
Addr HandlerBase;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
|
|
|
|
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
|
2009-07-21 10:09:05 +02:00
|
|
|
entryHi.asid = entryHiAsid;
|
|
|
|
entryHi.vpn2 = entryHiVPN2;
|
|
|
|
entryHi.vpn2x = entryHiVPN2X;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
|
|
|
|
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
|
2009-07-21 10:09:05 +02:00
|
|
|
context.badVPN2 = contextBadVPN2;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
|
2009-07-21 10:09:05 +02:00
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
|
2009-07-21 10:08:53 +02:00
|
|
|
// Since handler depends on EXL bit, must check EXL bit before setting it!!
|
|
|
|
// See MIPS ARM Vol 3, Revision 2, Page 38
|
2009-07-21 10:09:05 +02:00
|
|
|
if (status.exl == 1) {
|
2009-07-21 10:08:53 +02:00
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
} else {
|
|
|
|
// Offset 0x000
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
setExceptionState(tc, 0x2);
|
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
// Set new PC
|
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
Addr HandlerBase;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
|
|
|
|
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
|
2009-07-21 10:09:05 +02:00
|
|
|
entryHi.asid = entryHiAsid;
|
|
|
|
entryHi.vpn2 = entryHiVPN2;
|
|
|
|
entryHi.vpn2x = entryHiVPN2X;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
|
2009-07-21 10:09:05 +02:00
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
|
2009-07-21 10:09:05 +02:00
|
|
|
context.badVPN2 = contextBadVPN2;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
|
2009-07-21 10:09:05 +02:00
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
|
2009-07-21 10:08:53 +02:00
|
|
|
// Since handler depends on EXL bit, must check EXL bit before setting it!!
|
|
|
|
// See MIPS ARM Vol 3, Revision 2, Page 38
|
2009-07-21 10:09:05 +02:00
|
|
|
if (status.exl) {
|
2009-07-21 10:08:53 +02:00
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
} else {
|
|
|
|
// Offset 0x000
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
setExceptionState(tc, 0x3);
|
|
|
|
|
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
|
|
|
|
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
|
2009-07-21 10:09:05 +02:00
|
|
|
entryHi.asid = entryHiAsid;
|
|
|
|
entryHi.vpn2 = entryHiVPN2;
|
|
|
|
entryHi.vpn2x = entryHiVPN2X;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
|
2009-07-21 10:09:05 +02:00
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
|
2009-07-21 10:09:05 +02:00
|
|
|
context.badVPN2 = contextBadVPN2;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
|
2007-11-13 22:58:16 +01:00
|
|
|
|
|
|
|
// Set new PC
|
2009-07-21 10:08:53 +02:00
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setExceptionState(tc, 0x1);
|
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0x8);
|
2007-11-13 22:58:16 +01:00
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
// Set new PC
|
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
|
|
|
#if FULL_SYSTEM
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0x0A);
|
|
|
|
Addr HandlerBase;
|
|
|
|
|
2009-07-22 08:38:26 +02:00
|
|
|
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
|
2009-07-21 10:09:05 +02:00
|
|
|
if (cause.iv) {
|
2009-07-21 10:08:53 +02:00
|
|
|
// Offset 200 for release 2
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
} else {
|
|
|
|
//Ofset at 180 for release 1
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
}
|
2007-11-13 22:58:16 +01:00
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
2007-11-14 12:24:47 +01:00
|
|
|
#if FULL_SYSTEM
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
/* All reset activity must be invoked from here */
|
|
|
|
tc->setPC(vect());
|
|
|
|
tc->setNextPC(vect() + sizeof(MachInst));
|
|
|
|
tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
|
2009-07-21 10:09:05 +02:00
|
|
|
DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
|
2007-11-14 12:24:47 +01:00
|
|
|
#endif
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
// Set Coprocessor 1 (Floating Point) To Usable
|
2009-07-22 08:38:26 +02:00
|
|
|
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
|
2009-07-21 10:09:05 +02:00
|
|
|
status.cu.cu1 = 1;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscReg(MISCREG_STATUS, status);
|
2007-06-23 01:03:42 +02:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-06-23 01:03:42 +02:00
|
|
|
{
|
2007-11-13 22:58:16 +01:00
|
|
|
#if FULL_SYSTEM
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0x0A);
|
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase, tc);
|
2007-11-13 22:58:16 +01:00
|
|
|
#else
|
|
|
|
panic("%s encountered.\n", name());
|
|
|
|
#endif
|
2007-06-23 01:03:42 +02:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-06-23 01:03:42 +02:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
panic("%s encountered.\n", name());
|
2007-06-23 01:03:42 +02:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-06-23 01:03:42 +02:00
|
|
|
{
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
panic("%s encountered.\n", name());
|
2007-11-13 22:58:16 +01:00
|
|
|
}
|
|
|
|
|
2009-07-21 10:08:53 +02:00
|
|
|
void
|
2010-09-14 04:26:03 +02:00
|
|
|
CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
|
2007-11-13 22:58:16 +01:00
|
|
|
{
|
|
|
|
#if FULL_SYSTEM
|
2009-07-21 10:08:53 +02:00
|
|
|
DPRINTF(MipsPRA, "%s encountered.\n", name());
|
|
|
|
setExceptionState(tc, 0xb);
|
|
|
|
// The ID of the coprocessor causing the exception is stored in
|
|
|
|
// CoprocessorUnusableFault::coProcID
|
2009-07-22 08:38:26 +02:00
|
|
|
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
|
2009-07-21 10:09:05 +02:00
|
|
|
cause.ce = coProcID;
|
2009-07-22 08:38:26 +02:00
|
|
|
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
|
2009-07-21 10:08:53 +02:00
|
|
|
|
|
|
|
Addr HandlerBase;
|
|
|
|
// Offset 0x180 - General Exception Vector
|
2009-07-22 08:38:26 +02:00
|
|
|
HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
|
2009-07-21 10:08:53 +02:00
|
|
|
setHandlerPC(HandlerBase, tc);
|
|
|
|
|
2007-11-13 22:58:16 +01:00
|
|
|
#else
|
2007-11-14 12:24:47 +01:00
|
|
|
warn("%s (CP%d) encountered.\n", name(), coProcID);
|
2007-11-13 22:58:16 +01:00
|
|
|
#endif
|
2007-06-23 01:03:42 +02:00
|
|
|
}
|
|
|
|
|
2006-03-12 11:57:34 +01:00
|
|
|
} // namespace MipsISA
|
2006-02-22 04:02:05 +01:00
|
|
|
|