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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 47.496387 # Number of seconds simulated
sim_ticks 47496386980500 # Number of ticks simulated
final_tick 47496386980500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 708538 # Simulator instruction rate (inst/s)
host_op_rate 833484 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38555693115 # Simulator tick rate (ticks/s)
host_mem_usage 757988 # Number of bytes of host memory used
host_seconds 1231.89 # Real time elapsed on the host
sim_insts 872840522 # Number of instructions simulated
sim_ops 1026761155 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 77248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 78464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2962612 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 38823816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 12701504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 109824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 113728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2837560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 15245328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 12552128 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 438080 # Number of bytes read from this memory
system.physmem.bytes_read::total 85940292 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2962612 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2837560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5800172 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 72817088 # Number of bytes written to this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_written::total 72837672 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1207 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1226 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 86698 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 606635 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 198461 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1716 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1777 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 44425 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 238221 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 196127 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6845 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1383338 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1137767 # Number of write requests responded to by this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_writes::total 1140341 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1626 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 62376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 817406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 267420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2312 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2394 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 59743 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 320979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 264275 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1809407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 62376 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 59743 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 122118 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1533108 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_write::total 1533541 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1533108 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1626 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 62376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 817839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 267420 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2312 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 59743 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 320979 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 264275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3342948 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1383338 # Number of read requests accepted
system.physmem.writeReqs 1140341 # Number of write requests accepted
system.physmem.readBursts 1383338 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1140341 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 88503808 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 29824 # Total number of bytes read from write queue
system.physmem.bytesWritten 72836864 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 85940292 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 72837672 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 466 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 218501 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 80378 # Per bank write bursts
system.physmem.perBankRdBursts::1 85683 # Per bank write bursts
system.physmem.perBankRdBursts::2 84533 # Per bank write bursts
system.physmem.perBankRdBursts::3 91641 # Per bank write bursts
system.physmem.perBankRdBursts::4 87506 # Per bank write bursts
system.physmem.perBankRdBursts::5 92565 # Per bank write bursts
system.physmem.perBankRdBursts::6 85373 # Per bank write bursts
system.physmem.perBankRdBursts::7 87361 # Per bank write bursts
system.physmem.perBankRdBursts::8 80689 # Per bank write bursts
system.physmem.perBankRdBursts::9 125890 # Per bank write bursts
system.physmem.perBankRdBursts::10 79879 # Per bank write bursts
system.physmem.perBankRdBursts::11 87722 # Per bank write bursts
system.physmem.perBankRdBursts::12 73371 # Per bank write bursts
system.physmem.perBankRdBursts::13 83748 # Per bank write bursts
system.physmem.perBankRdBursts::14 77275 # Per bank write bursts
system.physmem.perBankRdBursts::15 79258 # Per bank write bursts
system.physmem.perBankWrBursts::0 66779 # Per bank write bursts
system.physmem.perBankWrBursts::1 71701 # Per bank write bursts
system.physmem.perBankWrBursts::2 72134 # Per bank write bursts
system.physmem.perBankWrBursts::3 76164 # Per bank write bursts
system.physmem.perBankWrBursts::4 73824 # Per bank write bursts
system.physmem.perBankWrBursts::5 77776 # Per bank write bursts
system.physmem.perBankWrBursts::6 71735 # Per bank write bursts
system.physmem.perBankWrBursts::7 72120 # Per bank write bursts
system.physmem.perBankWrBursts::8 69346 # Per bank write bursts
system.physmem.perBankWrBursts::9 71851 # Per bank write bursts
system.physmem.perBankWrBursts::10 68226 # Per bank write bursts
system.physmem.perBankWrBursts::11 73306 # Per bank write bursts
system.physmem.perBankWrBursts::12 64374 # Per bank write bursts
system.physmem.perBankWrBursts::13 72179 # Per bank write bursts
system.physmem.perBankWrBursts::14 67114 # Per bank write bursts
system.physmem.perBankWrBursts::15 69447 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.numWrRetry 52 # Number of times write queue was full causing retry
system.physmem.totGap 47496383920000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::3 25 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 1340113 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.writePktSize::6 1137767 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1131623 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 75605 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 35452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 30271 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 26331 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 23289 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 20581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 17115 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 14732 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 3112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 848 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 378 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 327 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::15 16550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 19449 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 48905 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 57076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 64173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 65524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 69411 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 70341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 73639 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 73241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 74463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 72846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 73821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 77361 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 71631 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 68870 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 66897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1594 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 987 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 158 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 866706 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 186.153496 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 114.409994 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 244.608227 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 521785 60.20% 60.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 170596 19.68% 79.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 55940 6.45% 86.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 28866 3.33% 89.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 19331 2.23% 91.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11894 1.37% 93.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9595 1.11% 94.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 9879 1.14% 95.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 38820 4.48% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 866706 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 64746 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.358308 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 318.389928 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 64744 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 64746 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 64746 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.577549 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.073829 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.807966 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 61438 94.89% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 935 1.44% 96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 457 0.71% 97.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 214 0.33% 97.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 283 0.44% 97.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 509 0.79% 98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 100 0.15% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 37 0.06% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 36 0.06% 98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 29 0.04% 98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 34 0.05% 98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 27 0.04% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 442 0.68% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 39 0.06% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 47 0.07% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 53 0.08% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 64746 # Writes before turning the bus around for reads
system.physmem.totQLat 34994473123 # Total ticks spent queuing
system.physmem.totMemAccLat 60923323123 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6914360000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25305.65 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 44055.65 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
system.physmem.readRowHits 1113162 # Number of row buffer hits during reads
system.physmem.writeRowHits 541079 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 47.54 # Row buffer hit rate for writes
system.physmem.avgGap 18820295.26 # Average gap between requests
system.physmem.pageHitRate 65.62 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3392073720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1850833875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5421273000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3772869840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1205451752805 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27440415505500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31762537091220 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.735925 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45648791331206 # Time in different power states
system.physmem_0.memoryStateTime::REF 1586008580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 261586624794 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 3160223640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1724328375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5365089600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3601862640 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1192319355510 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27451935144000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31760338786245 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.689642 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45667995849266 # Time in different power states
system.physmem_1.memoryStateTime::REF 1586008580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 242377776984 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.walker.walks 104839 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 104839 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10495 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79742 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 104830 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 0.171707 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 55.594229 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047 104829 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 104830 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 90246 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19548.112936 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18016.919113 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 12415.253011 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 89555 99.23% 99.23% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 591 0.65% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 29 0.03% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 90246 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -2134286464 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.271898 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 580308492 -27.19% -27.19% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 -2714594956 127.19% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -2134286464 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 79742 88.37% 88.37% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10495 11.63% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 90237 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 104839 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 104839 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90237 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90237 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 195076 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.read_hits 85272873 # DTB read hits
system.cpu0.dtb.read_misses 78883 # DTB read misses
system.cpu0.dtb.write_hits 76479493 # DTB write hits
system.cpu0.dtb.write_misses 25956 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 39585 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.prefetch_faults 4176 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.perms_faults 10186 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 85351756 # DTB read accesses
system.cpu0.dtb.write_accesses 76505449 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dtb.hits 161752366 # DTB hits
system.cpu0.dtb.misses 104839 # DTB misses
system.cpu0.dtb.accesses 161857205 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.itb.walker.walks 57460 # Table walker walks requested
system.cpu0.itb.walker.walksLong 57460 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 729 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51308 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 57460 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 57460 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 57460 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 52037 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 22020.322079 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 19981.613647 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 15973.969343 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 48320 92.86% 92.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 2946 5.66% 98.52% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 248 0.48% 98.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 406 0.78% 99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.82% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 33 0.06% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 52037 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 51308 98.60% 98.60% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 729 1.40% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 52037 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57460 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57460 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52037 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52037 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 109497 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 453477294 # ITB inst hits
system.cpu0.itb.inst_misses 57460 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 27698 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.itb.inst_accesses 453534754 # ITB inst accesses
system.cpu0.itb.hits 453477294 # DTB hits
system.cpu0.itb.misses 57460 # DTB misses
system.cpu0.itb.accesses 453534754 # DTB accesses
system.cpu0.numCycles 94992773961 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.committedInsts 453209687 # Number of instructions committed
system.cpu0.committedOps 531499422 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 488089676 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 379595 # Number of float alu accesses
system.cpu0.num_func_calls 26785883 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 68737200 # number of instructions that are conditional controls
system.cpu0.num_int_insts 488089676 # number of integer instructions
system.cpu0.num_fp_insts 379595 # number of float instructions
system.cpu0.num_int_register_reads 710027821 # number of times the integer registers were read
system.cpu0.num_int_register_writes 387728381 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 639718 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 261592 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 118698555 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 118319526 # number of times the CC registers were written
system.cpu0.num_mem_refs 161743236 # number of memory refs
system.cpu0.num_load_insts 85268904 # Number of load instructions
system.cpu0.num_store_insts 76474332 # Number of store instructions
system.cpu0.num_idle_cycles 93849963781.964020 # Number of idle cycles
system.cpu0.num_busy_cycles 1142810179.035976 # Number of busy cycles
system.cpu0.not_idle_fraction 0.012030 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.987970 # Percentage of idle cycles
system.cpu0.Branches 100837041 # Number of branches fetched
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.op_class::IntAlu 368748107 69.34% 69.34% # Class of executed instruction
system.cpu0.op_class::IntMult 1224660 0.23% 69.57% # Class of executed instruction
system.cpu0.op_class::IntDiv 64156 0.01% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 29994 0.01% 69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
system.cpu0.op_class::MemRead 85268904 16.03% 85.62% # Class of executed instruction
system.cpu0.op_class::MemWrite 76474332 14.38% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.op_class::total 531810153 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.kern.inst.quiesce 14069 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 5594005 # number of replacements
system.cpu0.dcache.tags.tagsinuse 472.878328 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 155905526 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5594517 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.867558 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 3986453000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.878328 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923590 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.923590 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 329066714 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 329066714 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 79426163 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 79426163 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 72239104 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 72239104 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186194 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 186194 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 137014 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 137014 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1774977 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1774977 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1742409 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1742409 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 151665267 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 151665267 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 151851461 # number of overall hits
system.cpu0.dcache.overall_hits::total 151851461 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3027243 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3027243 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1374655 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1374655 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667737 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 667737 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 757348 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 757348 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163489 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 163489 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194173 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 194173 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 4401898 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4401898 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 5069635 # number of overall misses
system.cpu0.dcache.overall_misses::total 5069635 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 43551375000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 43551375000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25743175500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 25743175500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46783649000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 46783649000 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2342479000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2342479000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4171693500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4171693500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2590500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2590500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 69294550500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 69294550500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 69294550500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 69294550500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 82453406 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 82453406 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73613759 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 73613759 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853931 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 853931 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894362 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 894362 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938466 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 1938466 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1936582 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1936582 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 156067165 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 156067165 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 156921096 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 156921096 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036715 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036715 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018674 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018674 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781957 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781957 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846803 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846803 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084339 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084339 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100266 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100266 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028205 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.028205 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032307 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.032307 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14386.481363 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14386.481363 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18727.008231 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18727.008231 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61772.988111 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61772.988111 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14328.052652 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14328.052652 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21484.415959 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21484.415959 # average StoreCondReq miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15741.970963 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15741.970963 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13668.548229 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13668.548229 # average overall miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.writebacks::writebacks 3814789 # number of writebacks
system.cpu0.dcache.writebacks::total 3814789 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30828 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21250 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 21250 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41671 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41671 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 52078 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 52078 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 52078 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 52078 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2996415 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 2996415 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1353405 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1353405 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 662134 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 662134 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 757348 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 757348 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121818 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121818 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194173 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 194173 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4349820 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4349820 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5011954 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5011954 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27090 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26689 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 53779 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39330539500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39330539500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23857005000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23857005000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13760399000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13760399000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 46026301000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 46026301000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1597973500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1597973500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3977579500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3977579500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2531500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2531500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63187544500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 63187544500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 76947943500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 76947943500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4585847500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4585847500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4300128500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4300128500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8885976000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8885976000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036341 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018385 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018385 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775395 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775395 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.846803 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.846803 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062842 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062842 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100266 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100266 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027871 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027871 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031939 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031939 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13125.865242 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13125.865242 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17627.395347 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17627.395347 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20781.894601 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20781.894601 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60772.988111 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60772.988111 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13117.712489 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13117.712489 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20484.719812 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20484.719812 # average StoreCondReq mshr miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14526.473394 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14526.473394 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15352.883027 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15352.883027 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169281.930602 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169281.930602 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161119.880850 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 161119.880850 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165231.335651 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165231.335651 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.replacements 4817420 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.881006 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 448659362 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 4817932 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 93.122809 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 42527405000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.881006 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999768 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.tag_accesses 911772520 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 911772520 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 448659362 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 448659362 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 448659362 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 448659362 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 448659362 # number of overall hits
system.cpu0.icache.overall_hits::total 448659362 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 4817932 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 4817932 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 4817932 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 4817932 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 4817932 # number of overall misses
system.cpu0.icache.overall_misses::total 4817932 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 51018469500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 51018469500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 51018469500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 51018469500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 51018469500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 51018469500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 453477294 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 453477294 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 453477294 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 453477294 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 453477294 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 453477294 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010624 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.010624 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010624 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.010624 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010624 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.010624 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10589.287997 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10589.287997 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10589.287997 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10589.287997 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10589.287997 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10589.287997 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4817932 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 4817932 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 4817932 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 4817932 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 4817932 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 4817932 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 48609503500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 48609503500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 48609503500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 48609503500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 48609503500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 48609503500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010624 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.010624 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.010624 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10089.287997 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7903007 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7903048 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 1031104 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2447325 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15787.482525 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 17072683 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2462926 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.931870 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 38930323500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 7763.481265 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.845053 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.926815 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3265.491531 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.056672 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1075.681189 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.473845 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003958 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005794 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.199310 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.215030 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065654 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.963591 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1662 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13857 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 291 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 746 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 625 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5813 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5388 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.101440 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.845764 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 352133802 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 352133802 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 213691 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 129371 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 343062 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 3814786 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 3814786 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 99833 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 99833 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 32914 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 32914 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 902621 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 902621 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4275985 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 4275985 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2838458 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2838458 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175241 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 175241 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 213691 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 129371 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 4275985 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3741079 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 8360126 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 213691 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 129371 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 4275985 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3741079 # number of overall hits
system.cpu0.l2cache.overall_hits::total 8360126 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9038 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7286 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 16324 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121358 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 121358 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 161252 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 161252 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 246467 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 246467 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 541947 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 541947 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 941909 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 941909 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 580933 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 580933 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9038 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7286 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 541947 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1188376 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 1746647 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9038 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7286 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 541947 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1188376 # number of overall misses
system.cpu0.l2cache.overall_misses::total 1746647 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 297968500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 261413000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 559381500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2650604000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 2650604000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3370536000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3370536000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2441998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2441998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11722428500 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 11722428500 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15931119500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15931119500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30566703000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30566703000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 43739049000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 43739049000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 297968500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 261413000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15931119500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 42289131500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 58779632500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 297968500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 261413000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15931119500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 42289131500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 58779632500 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222729 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136657 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 359386 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 3814786 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 3814786 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 221191 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 221191 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194166 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 194166 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1149088 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1149088 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4817932 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 4817932 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3780367 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 3780367 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 756174 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 756174 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222729 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136657 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 4817932 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 4929455 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 10106773 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222729 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136657 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 4817932 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 4929455 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 10106773 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053316 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.045422 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.548657 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.548657 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.830485 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.830485 # miss rate for SCUpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214489 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214489 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.112485 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.112485 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249158 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249158 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.768253 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.768253 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053316 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.112485 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241077 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.172819 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053316 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.112485 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241077 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.172819 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35878.808674 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34267.428326 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21841.197119 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21841.197119 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20902.289584 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20902.289584 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 348856.857143 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 348856.857143 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47561.858180 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47561.858180 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29396.083934 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29396.083934 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32451.864246 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32451.864246 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 75291.038726 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 75291.038726 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35878.808674 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29396.083934 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35585.649239 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 33652.840271 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35878.808674 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29396.083934 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35585.649239 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 33652.840271 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.writebacks::writebacks 1370697 # number of writebacks
system.cpu0.l2cache.writebacks::total 1370697 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4625 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 4625 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 320 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 320 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 4945 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 4945 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 4945 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 4945 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9038 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7286 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 16324 # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 97439 # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total 97439 # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 677798 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 677798 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121358 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121358 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 161252 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 161252 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 241842 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 241842 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 541947 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 541947 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 941589 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 941589 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 580933 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 580933 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9038 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7286 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 541947 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1183431 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 1741702 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9038 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7286 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 541947 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1183431 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 677798 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2419500 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70215 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26689 # number of WriteReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 96904 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 217697000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 461437500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28787351301 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 28787351301 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2500247000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2500247000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2505266500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2505266500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2087998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2087998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9802286000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9802286000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 12679437500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 12679437500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 24890887500 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 24890887500 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 40253451000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 40253451000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 217697000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12679437500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34693173500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 47834048500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 217697000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12679437500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34693173500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28787351301 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 76621399801 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4369127500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7823405000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4099961000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4099961000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8469088500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11923366000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045422 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548657 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548657 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.830485 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.830485 # mshr miss rate for SCUpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210464 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210464 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.112485 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249073 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249073 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.768253 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.768253 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240073 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172330 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240073 # mshr miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239394 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28267.428326 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42471.874070 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20602.242951 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20602.242951 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15536.343735 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15536.343735 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 298285.428571 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 298285.428571 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40531.776945 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40531.776945 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23396.083934 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26434.981186 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26434.981186 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69291.038726 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69291.038726 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29315.755207 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27463.968291 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29315.755207 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31668.278488 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161281.930602 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111420.707826 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153619.880850 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153619.880850 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157479.471541 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 123043.073557 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.trans_dist::ReadReq 556196 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 9235290 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 26689 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 7191964 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 8875110 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 964168 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 427001 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350742 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 480184 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1494626 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1158048 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4817932 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5665215 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 862902 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 756174 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14539205 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18068890 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 308145 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 526057 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 33442297 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 308520148 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 566266158 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1093256 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1781832 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 877661394 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 9623929 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 31244724 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.314212 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.464201 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::1 21427251 68.58% 68.58% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 9817473 31.42% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 31244724 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 14779167493 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 183875487 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 7270023000 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 8020770875 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 171488000 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 303329497 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.walker.walks 102079 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 102079 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8198 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78187 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 102062 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 0.078384 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 25.041362 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511 102061 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 102062 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 86402 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20584.963311 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18803.464379 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14594.922091 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 82288 95.24% 95.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3069 3.55% 98.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 485 0.56% 99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 417 0.48% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 31 0.04% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 11 0.01% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 86402 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -6989065760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.774297 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.418044 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1577450036 22.57% 22.57% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 -5411615724 77.43% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -6989065760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 78188 90.51% 90.51% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 8198 9.49% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 86386 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102079 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102079 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86386 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86386 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 188465 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.read_hits 79156855 # DTB read hits
system.cpu1.dtb.read_misses 74074 # DTB read misses
system.cpu1.dtb.write_hits 72945567 # DTB write hits
system.cpu1.dtb.write_misses 28005 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 34474 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.prefetch_faults 4171 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.perms_faults 9254 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 79230929 # DTB read accesses
system.cpu1.dtb.write_accesses 72973572 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dtb.hits 152102422 # DTB hits
system.cpu1.dtb.misses 102079 # DTB misses
system.cpu1.dtb.accesses 152204501 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.itb.walker.walks 60277 # Table walker walks requested
system.cpu1.itb.walker.walksLong 60277 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 437 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54558 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 60277 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 60277 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 60277 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 54995 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 23406.355123 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21056.017834 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18686.344458 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 50855 92.47% 92.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 2976 5.41% 97.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 347 0.63% 98.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 645 1.17% 99.69% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 26 0.05% 99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 61 0.11% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 54995 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1687858036 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1687858036 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1687858036 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 54558 99.21% 99.21% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 437 0.79% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 54995 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60277 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60277 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54995 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54995 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 115272 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 419908062 # ITB inst hits
system.cpu1.itb.inst_misses 60277 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 24325 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.itb.inst_accesses 419968339 # ITB inst accesses
system.cpu1.itb.hits 419908062 # DTB hits
system.cpu1.itb.misses 60277 # DTB misses
system.cpu1.itb.accesses 419968339 # DTB accesses
system.cpu1.numCycles 94992773961 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.committedInsts 419630835 # Number of instructions committed
system.cpu1.committedOps 495261733 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 455389756 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 523939 # Number of float alu accesses
system.cpu1.num_func_calls 25402387 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 63797614 # number of instructions that are conditional controls
system.cpu1.num_int_insts 455389756 # number of integer instructions
system.cpu1.num_fp_insts 523939 # number of float instructions
system.cpu1.num_int_register_reads 660733277 # number of times the integer registers were read
system.cpu1.num_int_register_writes 360799808 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 826391 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 485612 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 108763380 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 108525865 # number of times the CC registers were written
system.cpu1.num_mem_refs 152092816 # number of memory refs
system.cpu1.num_load_insts 79152639 # Number of load instructions
system.cpu1.num_store_insts 72940177 # Number of store instructions
system.cpu1.num_idle_cycles 94000482737.518021 # Number of idle cycles
system.cpu1.num_busy_cycles 992291223.481979 # Number of busy cycles
system.cpu1.not_idle_fraction 0.010446 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.989554 # Percentage of idle cycles
system.cpu1.Branches 93826575 # Number of branches fetched
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.op_class::IntAlu 342323632 69.08% 69.08% # Class of executed instruction
system.cpu1.op_class::IntMult 986133 0.20% 69.28% # Class of executed instruction
system.cpu1.op_class::IntDiv 54444 0.01% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 82001 0.02% 69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.31% # Class of executed instruction
system.cpu1.op_class::MemRead 79152639 15.97% 85.28% # Class of executed instruction
system.cpu1.op_class::MemWrite 72940177 14.72% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.op_class::total 495539069 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.kern.inst.quiesce 5086 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 4879882 # number of replacements
system.cpu1.dcache.tags.tagsinuse 454.664905 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 147036928 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 4880392 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 30.128098 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8391455352000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 454.664905 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888017 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.888017 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 309114667 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 309114667 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 73769374 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 73769374 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 69164773 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 69164773 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181014 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 181014 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 188653 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 188653 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1698614 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1698614 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1666903 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1666903 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 142934147 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 142934147 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 143115161 # number of overall hits
system.cpu1.dcache.overall_hits::total 143115161 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 2759570 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 2759570 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1240940 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1240940 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 581228 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 581228 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 477261 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 477261 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156018 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 156018 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186042 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 186042 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 4000510 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 4000510 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 4581738 # number of overall misses
system.cpu1.dcache.overall_misses::total 4581738 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39233003500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 39233003500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20835462500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 20835462500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14509055000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 14509055000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2381741000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2381741000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3985246000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 3985246000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1637000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1637000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 60068466000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 60068466000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 60068466000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 60068466000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 76528944 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 76528944 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 70405713 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 70405713 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 762242 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 762242 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 665914 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 665914 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1854632 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1854632 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1852945 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1852945 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 146934657 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 146934657 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 147696899 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 147696899 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036059 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.036059 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017626 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.017626 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762524 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762524 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716701 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716701 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084123 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084123 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100403 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100403 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027226 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.027226 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031021 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.031021 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14217.071319 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14217.071319 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16790.064387 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16790.064387 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 30400.671750 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 30400.671750 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.809073 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15265.809073 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21421.216715 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21421.216715 # average StoreCondReq miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15015.202062 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15015.202062 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13110.410504 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13110.410504 # average overall miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.writebacks::writebacks 3169454 # number of writebacks
system.cpu1.dcache.writebacks::total 3169454 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14967 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 14967 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 437 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 437 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44200 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44200 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 15404 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 15404 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 15404 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 15404 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2744603 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2744603 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1240503 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1240503 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 581228 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 581228 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 477261 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 477261 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111818 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111818 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186042 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 186042 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 3985106 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 3985106 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4566334 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4566334 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11055 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11055 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11308 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22363 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22363 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35762824500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35762824500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19580379500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19580379500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11426394500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11426394500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14031794000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14031794000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521108000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521108000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3799241000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3799241000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1600000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1600000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 55343204000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 55343204000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 66769598500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 66769598500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1911574500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1911574500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2027224500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2027224500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3938799000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3938799000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035864 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035864 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017619 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017619 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762524 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762524 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716701 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716701 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060291 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060291 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100403 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100403 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027122 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027122 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030917 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.030917 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13030.235885 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13030.235885 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15784.225834 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15784.225834 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19659.057203 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19659.057203 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 29400.671750 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 29400.671750 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13603.426997 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13603.426997 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20421.415594 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20421.415594 # average StoreCondReq mshr miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13887.511148 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13887.511148 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14622.145139 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14622.145139 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172914.925373 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172914.925373 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179273.478953 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179273.478953 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176130.170371 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 176130.170371 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.icache.tags.replacements 5061942 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.285809 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 414845603 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5062454 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 81.945555 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8391427807000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.285809 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969308 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969308 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.icache.tags.tag_accesses 844878583 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 844878583 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 414845603 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 414845603 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 414845603 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 414845603 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 414845603 # number of overall hits
system.cpu1.icache.overall_hits::total 414845603 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 5062459 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 5062459 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 5062459 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 5062459 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 5062459 # number of overall misses
system.cpu1.icache.overall_misses::total 5062459 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51775886000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 51775886000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 51775886000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 51775886000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 51775886000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 51775886000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 419908062 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 419908062 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 419908062 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 419908062 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 419908062 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 419908062 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012056 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.012056 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012056 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.012056 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012056 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.012056 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10227.418336 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10227.418336 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10227.418336 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10227.418336 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5062459 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5062459 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5062459 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5062459 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5062459 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5062459 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49244656500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 49244656500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49244656500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 49244656500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49244656500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 49244656500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9661500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9661500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9661500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9661500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012056 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.012056 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.012056 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9727.418336 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 87831.818182 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 87831.818182 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6553328 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6553344 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 818232 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 1797985 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13499.130791 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 17098114 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 1814056 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 9.425351 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 10027287971500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 5261.606925 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.626364 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 80.602782 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3547.198081 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3740.075738 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.020901 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.321143 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004555 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004920 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.216504 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.228276 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048524 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.823922 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1537 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14473 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 563 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 884 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4486 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5048 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3979 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.093811 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883362 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 335653129 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 335653129 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 217635 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 143511 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 361146 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 3169452 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 3169452 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 61375 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 61375 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 29429 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 29429 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 854276 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 854276 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4594945 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4594945 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2597133 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2597133 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 245829 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 245829 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 217635 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 143511 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4594945 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3451409 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8407500 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 217635 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 143511 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4594945 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3451409 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8407500 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9790 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8267 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 18057 # number of ReadReq misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120456 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 120456 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156608 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 156608 # number of SCUpgradeReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 206111 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 206111 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467514 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 467514 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 840516 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 840516 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 229973 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 229973 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9790 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8267 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 467514 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1046627 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1532198 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9790 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8267 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 467514 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1046627 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1532198 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 350581000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 322699500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 673280500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2589720500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 2589720500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3249045500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3249045500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1543999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1543999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8558602000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 8558602000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 14244872000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 14244872000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 26670955500 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 26670955500 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 11700893500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 11700893500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 350581000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 322699500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14244872000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 35229557500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 50147710000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 350581000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 322699500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14244872000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 35229557500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 50147710000 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 227425 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151778 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 379203 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 3169453 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 3169453 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 181831 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 181831 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 186037 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 186037 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1060387 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1060387 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5062459 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 5062459 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3437649 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3437649 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 475802 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 475802 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 227425 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151778 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 5062459 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4498036 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 9939698 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 227425 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151778 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 5062459 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4498036 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 9939698 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.054468 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.047618 # miss rate for ReadReq accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.662461 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.662461 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.841811 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.841811 # miss rate for SCUpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.194373 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.194373 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092349 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092349 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244503 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244503 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.483338 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.483338 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.054468 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092349 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.232685 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.154149 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.054468 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092349 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.232685 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.154149 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39034.655861 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37286.398627 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21499.306801 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21499.306801 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20746.357147 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20746.357147 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 308799.800000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 308799.800000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41524.236940 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41524.236940 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 30469.401986 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 30469.401986 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31731.645204 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31731.645204 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 50879.422802 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 50879.422802 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39034.655861 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30469.401986 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33660.088551 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32729.262145 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39034.655861 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30469.401986 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33660.088551 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32729.262145 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.writebacks::writebacks 868662 # number of writebacks
system.cpu1.l2cache.writebacks::total 868662 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5194 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 5194 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 348 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 348 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5542 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 5542 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5542 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 5542 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9790 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8267 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 18057 # number of ReadReq MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 85466 # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total 85466 # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 604026 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 604026 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120456 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120456 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 156608 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 156608 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 200917 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 200917 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 467514 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 467514 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 840168 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 840168 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 229971 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 229971 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9790 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8267 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 467514 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1041085 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1526656 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9790 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8267 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 467514 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1041085 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 604026 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2130682 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11055 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11165 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11308 # number of WriteReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22363 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 22473 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 273097500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 564938500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27533861444 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27533861444 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2500623000 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2500623000 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2389472000 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2389472000 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1321999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1321999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6820721500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6820721500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 11439788000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 11439788000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 21593362000 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 21593362000 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 10321018000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 10321018000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 273097500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 11439788000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 28414083500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 40418810000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 273097500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 11439788000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 28414083500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27533861444 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 67952671444 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8836500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1823134500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1831971000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1942414500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1942414500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8836500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3765549000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3774385500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.047618 # mshr miss rate for ReadReq accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.662461 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.662461 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.841811 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.841811 # mshr miss rate for SCUpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189475 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189475 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092349 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.244402 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244402 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.483333 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.483333 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231453 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153592 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231453 # mshr miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.214361 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31286.398627 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45583.901097 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.638374 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.638374 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15257.662444 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15257.662444 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 264399.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 264399.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33947.956121 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33947.956121 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24469.401986 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25701.243085 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25701.243085 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 44879.650043 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 44879.650043 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.388038 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31892.451076 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164914.925373 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164081.594268 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171773.478953 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171773.478953 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 168382.998703 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167952.009078 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::ReadReq 559173 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9082723 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11308 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 6546630 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 9047745 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 872762 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 38 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 399618 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347237 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 434764 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1786739 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1070352 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5062459 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5562594 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 582530 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 475802 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15186455 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15778247 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332058 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 524938 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 31821698 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 323997816 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 497415771 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1214224 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1819400 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 824447211 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 10229580 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 30806602 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.338828 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.473311 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::1 20368466 66.12% 66.12% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 10438136 33.88% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 30806602 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 13598256460 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 189037985 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 7593798500 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 7185863072 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 180280000 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 297513000 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::ReadReq 40323 # Transaction distribution
system.iobus.trans_dist::ReadResp 40323 # Transaction distribution
system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
system.iobus.trans_dist::WriteResp 136623 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231190 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231190 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count::total 353892 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338776 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338776 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size::total 7496591 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer27.occupancy 569692377 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer3.occupancy 147886000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.replacements 115590 # number of replacements
system.iocache.tags.tagsinuse 11.304878 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.warmup_cycle 9148728954000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.397645 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.907233 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.462353 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.244202 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.706555 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tag_accesses 1040712 # Number of tag accesses
system.iocache.tags.data_accesses 1040712 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_misses::realview.ide 8867 # number of demand (read+write) misses
system.iocache.demand_misses::total 8907 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_misses::realview.ide 8867 # number of overall misses
system.iocache.overall_misses::total 8907 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1652925028 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1658120028 # number of ReadReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12636024349 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12636024349 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1652925028 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1658489028 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1652925028 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1658489028 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_accesses::realview.ide 8867 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8907 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_accesses::realview.ide 8867 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8907 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186413.107928 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186221.925876 # average ReadReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118394.651347 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118394.651347 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 186200.631863 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 186200.631863 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 32852 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 3487 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.421279 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.writebacks::writebacks 106693 # number of writebacks
system.iocache.writebacks::total 106693 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 8867 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_mshr_misses::realview.ide 8867 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8907 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1209575028 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1212920028 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7299624349 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7299624349 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1209575028 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1213139028 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1209575028 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1213139028 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136413.107928 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136221.925876 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68394.651347 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68394.651347 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.replacements 1309168 # number of replacements
system.l2c.tags.tagsinuse 63754.864014 # Cycle average of tags in use
system.l2c.tags.total_refs 4916621 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1368931 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.591577 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 19091.859701 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.912894 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 155.127533 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3615.637235 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7840.243629 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.501182 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 220.931545 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 308.618632 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3602.401841 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 8895.404165 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11593.225658 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.291319 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001616 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002367 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.055170 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.119633 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127037 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003371 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004709 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.054968 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.135733 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.176899 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.972822 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 11100 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 48385 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 212 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 379 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 10509 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1364 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4701 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 42219 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.169373 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.738297 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 62372649 # Number of tag accesses
system.l2c.tags.data_accesses 62372649 # Number of data accesses
system.l2c.Writeback_hits::writebacks 2239360 # number of Writeback hits
system.l2c.Writeback_hits::total 2239360 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 30980 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 24512 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 55492 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 6081 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 5027 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11108 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 167543 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 144880 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 312423 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5175 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4181 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 498211 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 558223 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 295485 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 4952 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4009 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 423075 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 457635 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 236791 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2487737 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5175 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4181 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 498211 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 725766 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 295485 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4952 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4009 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 423075 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 602515 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 236791 # number of demand (read+write) hits
system.l2c.demand_hits::total 2800160 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5175 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4181 # number of overall hits
system.l2c.overall_hits::cpu0.inst 498211 # number of overall hits
system.l2c.overall_hits::cpu0.data 725766 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 295485 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4952 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4009 # number of overall hits
system.l2c.overall_hits::cpu1.inst 423075 # number of overall hits
system.l2c.overall_hits::cpu1.data 602515 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 236791 # number of overall hits
system.l2c.overall_hits::total 2800160 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 43560 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 41893 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 85453 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 11005 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 9001 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 20006 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 491114 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 139826 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 630940 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1207 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1226 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 43736 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 119131 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 198612 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1716 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1777 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 44439 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 101598 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 196208 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 709650 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1207 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1226 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 43736 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 610245 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 198612 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1716 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1777 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 44439 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 241424 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 196208 # number of demand (read+write) misses
system.l2c.demand_misses::total 1340590 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1207 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1226 # number of overall misses
system.l2c.overall_misses::cpu0.inst 43736 # number of overall misses
system.l2c.overall_misses::cpu0.data 610245 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 198612 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1716 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1777 # number of overall misses
system.l2c.overall_misses::cpu1.inst 44439 # number of overall misses
system.l2c.overall_misses::cpu1.data 241424 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 196208 # number of overall misses
system.l2c.overall_misses::total 1340590 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 242100000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 225831000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 467931000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53618000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45210000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 98828000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 41035187500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 11309941500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 52345129000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 108698500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 110530000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3653235500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 10597934000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 150819000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 156924500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3723508500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 8959752500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 74608061217 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 108698500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 110530000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 3653235500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 51633121500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 150819000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 156924500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 3723508500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 20269694000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 126953190217 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 108698500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 110530000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 3653235500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 51633121500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 150819000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 156924500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 3723508500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 20269694000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of overall miss cycles
system.l2c.overall_miss_latency::total 126953190217 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 2239360 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 2239360 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 74540 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 66405 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 140945 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 17086 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 14028 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 31114 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 658657 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 284706 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 943363 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6382 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5407 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 541947 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 677354 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 494097 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6668 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5786 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 467514 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 559233 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 432999 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3197387 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 6382 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 5407 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 541947 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1336011 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 494097 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 6668 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5786 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 467514 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 843939 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 432999 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4140750 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 6382 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 5407 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 541947 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1336011 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 494097 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 6668 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5786 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 467514 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 843939 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 432999 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4140750 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584384 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.630871 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.606286 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.644095 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.641645 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.642990 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.745629 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.491124 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.668820 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.226743 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.080702 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.175877 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.307121 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.095054 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181674 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.221947 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.226743 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.080702 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.456766 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.307121 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.095054 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.286068 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.323755 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.226743 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.080702 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.456766 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.307121 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.095054 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.286068 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.323755 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5557.851240 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5390.661924 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5475.887330 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4872.149023 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5022.775247 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 4939.918025 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83555.320150 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80885.825955 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 82963.719213 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90154.975530 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83529.255076 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88960.337779 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88308.666292 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83789.205428 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88188.276344 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 105133.602786 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90154.975530 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 83529.255076 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 84610.478578 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88308.666292 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83789.205428 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83958.902180 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 94699.490685 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90154.975530 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 83529.255076 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 84610.478578 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88308.666292 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83789.205428 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83958.902180 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 94699.490685 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 67 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.writebacks::writebacks 1031074 # number of writebacks
system.l2c.writebacks::total 1031074 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 126 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 17 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 108 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 18 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 126 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 108 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 126 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 108 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 39567 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 39567 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 43560 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 41893 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 85453 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11005 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9001 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 20006 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 491114 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 139826 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 630940 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1207 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1226 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 43610 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 119114 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1716 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1777 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44331 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101580 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 709381 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1207 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1226 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 43610 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 610228 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1716 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1777 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 44331 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 241406 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 1340321 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1207 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1226 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 43610 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 610228 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1716 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1777 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 44331 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 241406 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 1340321 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11053 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 81378 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 37997 # number of WriteReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22361 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 119375 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 904276500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 870415500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1774692000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 228388000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 186718499 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 415106499 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 36124047500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 9911681500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 46035729000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 98270000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3207900500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9405362000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 139154500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3272125000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7942788500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 67494346717 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 98270000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 3207900500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 45529409500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 139154500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3272125000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 17854470000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 113530075717 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 98270000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 3207900500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 45529409500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 139154500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3272125000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 17854470000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 113530075717 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3881489500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6856500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1624141500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 8190514500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3646235000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1750167000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5396402000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7527724500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6856500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3374308500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 13586916500 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584384 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.630871 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.606286 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644095 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.641645 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.642990 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.745629 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.491124 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.668820 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.175852 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.181642 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.221863 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.456754 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.286047 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.323690 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.456754 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.286047 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.323690 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.331956 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20777.110734 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20768.047933 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20753.112222 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20744.194978 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20749.100220 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73555.320150 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70885.825955 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72963.719213 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78961.012140 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78192.444379 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95145.410882 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74610.489030 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74610.489030 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143281.266150 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146941.237673 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100647.773354 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136619.393758 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154772.461974 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142021.791194 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139975.166887 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150901.502616 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 113817.101571 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 81378 # Transaction distribution
system.membus.trans_dist::ReadResp 799663 # Transaction distribution
system.membus.trans_dist::WriteReq 37997 # Transaction distribution
system.membus.trans_dist::WriteResp 37997 # Transaction distribution
system.membus.trans_dist::Writeback 1137767 # Transaction distribution
system.membus.trans_dist::CleanEvict 200903 # Transaction distribution
system.membus.trans_dist::UpgradeReq 374437 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 306668 # Transaction distribution
system.membus.trans_dist::UpgradeResp 111797 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 646745 # Transaction distribution
system.membus.trans_dist::ReadExResp 624605 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 718285 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24438 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4799197 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4946349 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342551 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342551 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5288900 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48876 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 151511532 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 151716341 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7266432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 158982773 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 594252 # Total snoops (count)
system.membus.snoop_fanout::samples 3613210 # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::1 3613210 100.00% 100.00% # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 3613210 # Request fanout histogram
system.membus.reqLayer0.occupancy 101221000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer2.occupancy 21240500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer5.occupancy 7773596350 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer2.occupancy 7468178118 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer3.occupancy 229090524 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::ReadReq 81380 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4075375 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 37997 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 3377178 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1228761 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 423594 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 317776 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 741370 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1071890 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1071890 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4001246 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7774731 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5765311 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 13540042 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240674354 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 168156931 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 408831285 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3034988 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 11680683 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.131880 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.338360 # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::1 10140239 86.81% 86.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1540444 13.19% 100.00% # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::total 11680683 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 7606203373 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoopLayer0.occupancy 2481000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer0.occupancy 4538781481 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer1.occupancy 3532073491 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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