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gem5/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt

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test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
---------- Begin Simulation Statistics ----------
O3: Update stats for fetch and bp changes.
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sim_seconds 0.000011 # Number of seconds simulated
O3: Update stats for LSQ changes.
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sim_ticks 10910500 # Number of ticks simulated
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
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sim_freq 1000000000000 # Frequency of simulated ticks
O3: Update stats for LSQ changes.
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host_inst_rate 31106 # Simulator instruction rate (inst/s)
host_tick_rate 58503850 # Simulator tick rate (ticks/s)
host_mem_usage 241340 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
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sim_insts 5800 # Number of instructions simulated
O3: Update stats for fetch and bp changes.
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system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
O3: Update stats for LSQ changes.
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system.cpu.numCycles 21822 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.BPredUnit.lookups 2297 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted
O3: Update stats for fetch and bp changes.
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system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect
O3: Update stats for LSQ changes.
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system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
O3: Update stats for LSQ changes.
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system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for LSQ changes.
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system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
O3: Update stats for LSQ changes.
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system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2045 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing
O3: Update stats for fetch and bp changes.
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system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction
O3: Update stats for LSQ changes.
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system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode
O3: Update stats for fetch and bp changes.
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system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode
O3: Update stats for LSQ changes.
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system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking
O3: Update stats for fetch and bp changes.
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system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst
O3: Update stats for LSQ changes.
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system.cpu.rename.RunCycles 1920 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename
O3: Update stats for fetch and bp changes.
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system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
O3: Update stats for LSQ changes.
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system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups
O3: Update stats for fetch and bp changes.
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system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing
O3: Update stats for fetch and bp changes.
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system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
O3: Update stats for fetch and bp changes.
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system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores.
O3: Update stats for LSQ changes.
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system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec)
O3: Update stats for fetch and bp changes.
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system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ
O3: Update stats for LSQ changes.
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system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued
O3: Update stats for fetch and bp changes.
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system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
O3: Update stats for LSQ changes.
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system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph
O3: Update stats for fetch and bp changes.
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system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed
O3: Update stats for LSQ changes.
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system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
O3: Update stats for LSQ changes.
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system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
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system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
O3: Update stats for LSQ changes.
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system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
O3: Update stats for LSQ changes.
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system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
O3: Update stats for LSQ changes.
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system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.FU_type_0::total 8536 # Type of FU issued
system.cpu.iq.rate 0.391165 # Inst issue rate
system.cpu.iq.fu_busy_cnt 154 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses
O3: Update stats for fetch and bp changes.
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system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses
O3: Update stats for LSQ changes.
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system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
O3: Update stats for LSQ changes.
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system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
O3: Update stats for LSQ changes.
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system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.exec_refs 2952 # number of memory reference insts executed
system.cpu.iew.exec_branches 1313 # Number of branches executed
system.cpu.iew.exec_stores 1341 # Number of stores executed
system.cpu.iew.exec_rate 0.374393 # Inst execution rate
system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7879 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4173 # num instructions producing a value
system.cpu.iew.wb_consumers 6691 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.count 5800 # Number of instructions committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2008 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 962 # Number of loads committed
system.cpu.commit.membars 7 # Number of memory barriers committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.branches 1038 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5706 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rob.rob_reads 19701 # The number of ROB reads
system.cpu.rob.rob_writes 20673 # The number of ROB writes
system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.committedInsts 5800 # Number of Instructions Simulated
system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads
system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12979 # number of integer regfile reads
system.cpu.int_regfile_writes 6957 # number of integer regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fp_regfile_reads 28 # number of floating regfile reads
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use
system.cpu.icache.total_refs 1291 # Total number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits
system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits
system.cpu.icache.overall_hits 1291 # number of overall hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses
system.cpu.icache.demand_misses 420 # number of demand (read+write) misses
system.cpu.icache.overall_misses 420 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use
system.cpu.dcache.total_refs 2156 # Total number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.occ_blocks::0 66.296919 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.016186 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 728 # number of WriteReq hits
system.cpu.dcache.demand_hits 2156 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 2156 # number of overall hits
system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 318 # number of WriteReq misses
system.cpu.dcache.demand_misses 406 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 406 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2947000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 10802500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 13749500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 13749500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses)
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_accesses 2562 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 2562 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.058047 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.304015 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.158470 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.158470 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 33865.763547 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33865.763547 # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 0 # number of writebacks
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.WriteReq_mshr_miss_latency 1751000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3714500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3714500 # number of overall MSHR miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate 0.037599 # mshr miss rate for ReadReq accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_mshr_miss_rate 0.040984 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.040984 # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421 # average ReadReq mshr miss latency
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36479.166667 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.occ_blocks::0 200.613051 # Average occupied blocks per context
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits
system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 9 # number of overall hits
system.cpu.l2cache.ReadReq_misses 399 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 447 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 447 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 13714000 # number of ReadReq miss cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.ReadExReq_miss_latency 1678500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 15392500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 15392500 # number of overall miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_accesses 456 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 456 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.977941 # miss rate for ReadReq accesses
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_miss_rate 0.980263 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34435.123043 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34435.123043 # average overall miss latency
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.writebacks 0 # number of writebacks
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_mshr_misses 399 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency 12434000 # number of ReadReq MSHR miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.demand_mshr_miss_latency 13960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 13960000 # number of overall MSHR miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
---------- End Simulation Statistics ----------
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