2004-01-22 02:14:10 +01:00
|
|
|
/*
|
2005-06-05 11:16:00 +02:00
|
|
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
2004-01-22 02:14:10 +01:00
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
2005-06-05 05:56:53 +02:00
|
|
|
/** @file
|
|
|
|
* Tsunami PCI interface CSRs
|
2004-01-22 02:14:10 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __TSUNAMI_PCHIP_HH__
|
|
|
|
#define __TSUNAMI_PCHIP_HH__
|
|
|
|
|
|
|
|
#include "dev/tsunami.hh"
|
2004-06-10 19:30:58 +02:00
|
|
|
#include "base/range.hh"
|
|
|
|
#include "dev/io_device.hh"
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2005-09-12 09:01:43 +02:00
|
|
|
class MemoryController;
|
|
|
|
|
2005-06-05 05:56:53 +02:00
|
|
|
/**
|
|
|
|
* A very simple implementation of the Tsunami PCI interface chips.
|
2004-01-22 02:14:10 +01:00
|
|
|
*/
|
2004-06-10 19:30:58 +02:00
|
|
|
class TsunamiPChip : public PioDevice
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-02-10 06:19:43 +01:00
|
|
|
private:
|
2004-05-30 23:45:46 +02:00
|
|
|
/** The base address of this device */
|
2004-02-10 06:19:43 +01:00
|
|
|
Addr addr;
|
2004-05-30 23:45:46 +02:00
|
|
|
|
|
|
|
/** The size of mappad from the above address */
|
2004-02-10 06:19:43 +01:00
|
|
|
static const Addr size = 0xfff;
|
2004-01-22 02:14:10 +01:00
|
|
|
|
|
|
|
protected:
|
2004-05-30 23:45:46 +02:00
|
|
|
/**
|
|
|
|
* pointer to the tsunami object.
|
|
|
|
* This is our access to all the other tsunami
|
|
|
|
* devices.
|
|
|
|
*/
|
2004-01-22 02:14:10 +01:00
|
|
|
Tsunami *tsunami;
|
|
|
|
|
2004-06-03 23:48:05 +02:00
|
|
|
/** Pchip control register */
|
|
|
|
uint64_t pctl;
|
|
|
|
|
2004-05-30 23:45:46 +02:00
|
|
|
/** Window Base addresses */
|
2004-02-22 02:29:38 +01:00
|
|
|
uint64_t wsba[4];
|
2004-05-30 23:45:46 +02:00
|
|
|
|
|
|
|
/** Window masks */
|
2004-02-22 02:29:38 +01:00
|
|
|
uint64_t wsm[4];
|
2004-05-30 23:45:46 +02:00
|
|
|
|
|
|
|
/** Translated Base Addresses */
|
2004-02-22 02:29:38 +01:00
|
|
|
uint64_t tba[4];
|
2004-01-22 02:14:10 +01:00
|
|
|
|
|
|
|
public:
|
2004-05-30 23:45:46 +02:00
|
|
|
/**
|
|
|
|
* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
|
|
|
|
* @param name the name of thes device
|
|
|
|
* @param t a pointer to the tsunami device
|
|
|
|
* @param a the address which we respond to
|
|
|
|
* @param mmu the mmu we are to register with
|
2004-06-10 19:30:58 +02:00
|
|
|
* @param hier object to store parameters universal the device hierarchy
|
|
|
|
* @param bus The bus that this device is attached to
|
2004-05-30 23:45:46 +02:00
|
|
|
*/
|
2004-02-10 06:19:43 +01:00
|
|
|
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
|
2005-11-20 22:57:53 +01:00
|
|
|
MemoryController *mmu, HierParams *hier, Bus *pio_bus,
|
2004-07-13 04:58:22 +02:00
|
|
|
Tick pio_latency);
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-05-30 23:45:46 +02:00
|
|
|
/**
|
|
|
|
* Translate a PCI bus address to a memory address for DMA.
|
|
|
|
* @todo Andrew says this needs to be fixed. What's wrong with it?
|
|
|
|
* @param busAddr PCI address to translate.
|
|
|
|
* @return memory system address
|
|
|
|
*/
|
2004-02-22 02:29:38 +01:00
|
|
|
Addr translatePciToDma(Addr busAddr);
|
|
|
|
|
2004-05-30 23:45:46 +02:00
|
|
|
/**
|
|
|
|
* Process a read to the PChip.
|
|
|
|
* @param req Contains the address to read from.
|
|
|
|
* @param data A pointer to write the read data to.
|
|
|
|
* @return The fault condition of the access.
|
|
|
|
*/
|
2004-02-03 22:59:40 +01:00
|
|
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
2004-05-30 23:45:46 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Process a write to the PChip.
|
|
|
|
* @param req Contains the address to write to.
|
|
|
|
* @param data The data to write.
|
|
|
|
* @return The fault condition of the access.
|
|
|
|
*/
|
2004-02-03 22:59:40 +01:00
|
|
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-05-30 23:45:46 +02:00
|
|
|
/**
|
|
|
|
* Serialize this object to the given output stream.
|
|
|
|
* @param os The stream to serialize to.
|
|
|
|
*/
|
2004-01-22 02:14:10 +01:00
|
|
|
virtual void serialize(std::ostream &os);
|
2004-05-30 23:45:46 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Reconstruct the state of this object from a checkpoint.
|
|
|
|
* @param cp The checkpoint use.
|
|
|
|
* @param section The section name of this object
|
|
|
|
*/
|
2004-01-22 02:14:10 +01:00
|
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
2004-06-10 19:30:58 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Return how long this access will take.
|
|
|
|
* @param req the memory request to calcuate
|
|
|
|
* @return Tick when the request is done
|
|
|
|
*/
|
|
|
|
Tick cacheAccess(MemReqPtr &req);
|
2004-01-22 02:14:10 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif // __TSUNAMI_PCHIP_HH__
|