gem5/arch/mips/isa/formats/fp.isa

// -*- mode:c++ -*-

////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//

output header {{
        /**
         * Base class for FP operations.
         */
        class FPOp : public MipsStaticInst
        {
                protected:

                /// Constructor
                FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };
}};

output decoder {{
        std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
                return "Disassembly of integer instruction\n";
        }
}};

def template FloatingPointExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
        {
                //These are set to constants when the execute method
                //is generated
                bool useCc = ;
                bool checkPriv = ;

                //Attempt to execute the instruction
                try
                {
                        checkPriv;

                        %(op_decl)s;
                        %(op_rd)s;
                        %(code)s;
                }
                //If we have an exception for some reason,
                //deal with it
                catch(MipsException except)
                {
                        //Deal with exception
                        return No_Fault;
                }

                //Write the resulting state to the execution context
                %(op_wb)s;
                if(useCc)
                {
                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
                }
                return No_Fault;
        }
}};

// Primary format for integer operate instructions:
def format FloatOp(code, *flags) {{
        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};

// Primary format for integer operate instructions:
def format Float64Op(code, *flags) {{
        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};