2006-09-01 23:59:36 +02:00
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|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
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|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-03-25 07:05:48 +02:00
|
|
|
global.BPredUnit.BTBHits 669 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 2338 # Number of BTB lookups
|
2006-10-14 00:59:29 +02:00
|
|
|
global.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions.
|
2006-11-12 17:07:34 +01:00
|
|
|
global.BPredUnit.condIncorrect 437 # Number of conditional branches incorrect
|
2007-03-25 07:05:48 +02:00
|
|
|
global.BPredUnit.condPredicted 1559 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 5224 # Number of BP lookups
|
2006-11-12 17:07:34 +01:00
|
|
|
global.BPredUnit.usedRAS 2821 # Number of times the RAS was used to get a target.
|
2007-03-25 07:05:48 +02:00
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|
|
host_inst_rate 12539 # Simulator instruction rate (inst/s)
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|
|
|
|
host_mem_usage 156028 # Number of bytes of host memory used
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|
|
|
|
host_seconds 0.45 # Real time elapsed on the host
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|
|
|
|
host_tick_rate 3120138 # Simulator tick rate (ticks/s)
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|
|
|
|
memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads.
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|
|
|
|
memdepunit.memDep.conflictingStores 12 # Number of conflicting stores.
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|
|
|
|
memdepunit.memDep.insertedLoads 3770 # Number of loads inserted to the mem dependence unit.
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|
|
|
|
memdepunit.memDep.insertedStores 3723 # Number of stores inserted to the mem dependence unit.
|
2006-09-01 23:59:36 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 5623 # Number of instructions simulated
|
2006-10-14 00:59:29 +02:00
|
|
|
sim_seconds 0.000001 # Number of seconds simulated
|
2007-03-25 07:05:48 +02:00
|
|
|
sim_ticks 1400134 # Number of ticks simulated
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:branches 862 # Number of branches committed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-03-25 07:05:48 +02:00
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|
|
system.cpu.commit.COM:committed_per_cycle.samples 52214
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-03-25 07:05:48 +02:00
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|
|
0 49499 9480.02%
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|
|
1 1576 301.83%
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|
|
|
|
2 483 92.50%
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|
|
|
|
3 233 44.62%
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|
|
|
|
4 133 25.47%
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|
|
|
|
5 102 19.53%
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|
|
|
|
6 60 11.49%
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|
|
|
|
7 27 5.17%
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|
|
|
|
8 101 19.34%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
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|
|
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|
|
system.cpu.commit.COM:count 5640 # Number of instructions committed
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|
|
|
|
system.cpu.commit.COM:loads 979 # Number of loads committed
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|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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|
|
|
|
system.cpu.commit.COM:refs 1791 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.commit.branchMispredicts 368 # The number of times a branch was mispredicted
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2007-03-25 07:05:48 +02:00
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|
|
system.cpu.commit.commitSquashedInsts 13804 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts 5623 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
|
2007-03-25 07:05:48 +02:00
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|
|
system.cpu.cpi 249.001245 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 249.001245 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 1596 # number of ReadReq accesses(hits+misses)
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 6986.684848 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6882.626263 # average ReadReq mshr miss latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 1431 # number of ReadReq hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency 1152803 # number of ReadReq miss cycles
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.103383 # miss rate for ReadReq accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses 165 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 681380 # number of ReadReq MSHR miss cycles
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.062030 # mshr miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
|
2006-10-07 18:58:37 +02:00
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|
|
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
2007-03-25 07:05:48 +02:00
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|
|
system.cpu.dcache.WriteReq_avg_miss_latency 5293.200787 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5141.095890 # average WriteReq mshr miss latency
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.dcache.WriteReq_hits 558 # number of WriteReq hits
|
2007-03-25 07:05:48 +02:00
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|
|
system.cpu.dcache.WriteReq_miss_latency 1344473 # number of WriteReq miss cycles
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.312808 # miss rate for WriteReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_misses 254 # number of WriteReq misses
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|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 181 # number of WriteReq MSHR hits
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 375300 # number of WriteReq MSHR miss cycles
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
2007-01-23 08:44:44 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 3366.930233 # average number of cycles each access was blocked
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|
|
|
|
system.cpu.dcache.avg_refs 11.563953 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.blocked_no_targets 43 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 144778 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.demand_accesses 2408 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 5960.085919 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 6143.488372 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 1989 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 2497276 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.174003 # miss rate for demand accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.dcache.demand_misses 419 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 247 # number of demand (read+write) MSHR hits
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 1056680 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.071429 # mshr miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.overall_accesses 2408 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 5960.085919 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 6143.488372 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.overall_hits 1989 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 2497276 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.174003 # miss rate for overall accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.dcache.overall_misses 419 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 247 # number of overall MSHR hits
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1056680 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.071429 # mshr miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.dcache.tagsinuse 101.349670 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1989 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 17501 # Number of cycles decode is blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.decode.DECODE:BranchResolved 167 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 29609 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 29114 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 5540 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 2527 # Number of cycles decode is squashing
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.decode.DECODE:UnblockCycles 60 # Number of cycles decode is unblocking
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.fetch.Branches 5224 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 6367 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 13308 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 35526 # Number of instructions fetch has processed
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.fetch.SquashCycles 2057 # Number of cycles fetch has spent squashing
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.fetch.branchRate 0.095429 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 7360 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 3490 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.648972 # Number of inst fetches per cycle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 54742
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-03-25 07:05:48 +02:00
|
|
|
0 47805 8732.78%
|
|
|
|
|
1 199 36.35%
|
|
|
|
|
2 500 91.34%
|
|
|
|
|
3 1426 260.49%
|
|
|
|
|
4 1459 266.52%
|
|
|
|
|
5 244 44.57%
|
|
|
|
|
6 327 59.73%
|
|
|
|
|
7 1225 223.78%
|
|
|
|
|
8 1557 284.43%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 6366 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5085.923937 # average ReadReq miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4278.032258 # average ReadReq mshr miss latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 5919 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 2273408 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.070217 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 447 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 137 # number of ReadReq MSHR hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 1326190 # number of ReadReq MSHR miss cycles
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.048696 # mshr miss rate for ReadReq accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets 3443.500000 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 19.093548 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.blocked_no_targets 8 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 27548 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.demand_accesses 6366 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5085.923937 # average overall miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4278.032258 # average overall mshr miss latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.demand_hits 5919 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 2273408 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.070217 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 447 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 137 # number of demand (read+write) MSHR hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 1326190 # number of demand (read+write) MSHR miss cycles
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.048696 # mshr miss rate for demand accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.overall_accesses 6366 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5085.923937 # average overall miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4278.032258 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.overall_hits 5919 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 2273408 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.070217 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 447 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 137 # number of overall MSHR hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 1326190 # number of overall MSHR miss cycles
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.048696 # mshr miss rate for overall accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.icache.tagsinuse 147.070711 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 5919 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.idleCycles 1345393 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 2362 # Number of branches executed
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.EXEC:nop 48 # number of nop insts executed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.EXEC:rate 0.247123 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 5464 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 2131 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.WB:consumers 6466 # num instructions consuming a value
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.WB:count 11625 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.798948 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.WB:producers 5166 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.212360 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 11698 # cumulative count of insts sent to commit
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 3770 # Number of dispatched load instructions
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 2547 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 3723 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 19439 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 3333 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 13528 # Number of executed instructions
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 2527 # Number of cycles IEW is squashing
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 1656 # Number of times an access to memory failed due to the cache being blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 61 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 2791 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 2911 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 61 # Number of memory order violations
|
2007-01-23 08:44:44 +01:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.ipc 0.004016 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.004016 # IPC: Total IPC of All Threads
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0 13833 # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-11-06 02:42:05 +01:00
|
|
|
(null) 2 0.01% # Type of FU issued
|
2007-03-25 07:05:48 +02:00
|
|
|
IntAlu 8240 59.57% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IntMult 1 0.01% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 2 0.01% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-03-25 07:05:48 +02:00
|
|
|
MemRead 3428 24.78% # Type of FU issued
|
|
|
|
|
MemWrite 2160 15.61% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.006289 # FU busy rate (busy events/executed inst)
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2007-03-25 07:05:48 +02:00
|
|
|
IntAlu 1 1.15% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-03-25 07:05:48 +02:00
|
|
|
MemRead 54 62.07% # attempts to use FU when none available
|
|
|
|
|
MemWrite 32 36.78% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 54742
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-03-25 07:05:48 +02:00
|
|
|
0 47874 8745.39%
|
|
|
|
|
1 3270 597.35%
|
|
|
|
|
2 1302 237.84%
|
|
|
|
|
3 1673 305.62%
|
|
|
|
|
4 327 59.73%
|
|
|
|
|
5 188 34.34%
|
|
|
|
|
6 75 13.70%
|
|
|
|
|
7 22 4.02%
|
|
|
|
|
8 11 2.01%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.252694 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 19367 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 13833 # Number of instructions issued
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 13339 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 9527 # Number of squashed operands that are examined and possibly removed from graph
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 480 # number of ReadReq accesses(hits+misses)
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4520.693750 # average ReadReq miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2303.372917 # average ReadReq mshr miss latency
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 2169933 # number of ReadReq miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses 480 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1105619 # number of ReadReq MSHR miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 480 # number of ReadReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4520.693750 # average overall miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 2169933 # number of demand (read+write) miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 1105619 # number of demand (read+write) MSHR miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4520.693750 # average overall miss latency
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 2169933 # number of overall miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 1105619 # number of overall MSHR miss cycles
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 480 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 248.469469 # Cycle average of tags in use
|
2006-11-23 02:20:38 +01:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.numCycles 54742 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 7851 # Number of cycles rename is blocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 29263 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 458 # Number of times rename has blocked due to LSQ full
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 35953 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 29156 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 20115 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 5451 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 2527 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 486 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 16064 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 831 # count of insts added to the skid buffer
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.timesIdled 369 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
