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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
sim_seconds 2.543311 # Number of seconds simulated
sim_ticks 2543310963000 # Number of ticks simulated
final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
host_inst_rate 64896 # Simulator instruction rate (inst/s)
host_op_rate 83503 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2736674491 # Simulator tick rate (ticks/s)
host_mem_usage 401948 # Number of bytes of host memory used
host_seconds 929.34 # Real time elapsed on the host
sim_insts 60310426 # Number of instructions simulated
sim_ops 77602848 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bytes_read::cpu0.inst 505600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4226512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 293504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4868124 # Number of bytes read from this memory
system.physmem.bytes_read::total 131007148 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 505600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 293504 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3786304 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1344512 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1671600 # Number of bytes written to this memory
system.physmem.bytes_written::total 6802416 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.num_reads::cpu0.inst 7900 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 66073 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 76071 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293491 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59161 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 336128 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 417900 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813189 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47619237 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bw_read::cpu0.inst 198796 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1661815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 115402 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1914089 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51510472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 198796 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 115402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314198 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1488730 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 528646 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 657253 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2674630 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1488730 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47619237 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bw_total::cpu0.inst 198796 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2190461 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 115402 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2571343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54185102 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293491 # Total number of read requests seen
system.physmem.writeReqs 813189 # Total number of write requests seen
system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978783424 # Total number of bytes read from memory
system.physmem.bytesWritten 52044096 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131007148 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6802416 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4673 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955732 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955447 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955562 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 956165 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956089 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956033 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955432 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50412 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50901 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50804 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50730 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.numWrRetry 32475 # Number of times wr buffer was full causing retry
system.physmem.totGap 2543309787500 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::2 43 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.readPktSize::6 154632 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754028 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.writePktSize::6 59161 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1054822 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 991773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 961430 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3605165 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2718295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2722207 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2700301 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 59966 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 59368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 110015 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 160547 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 109964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 9981 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 9914 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 10593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 9111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.wrQLenPdf::0 2745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2865 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2928 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2923 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2923 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32768 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests
system.physmem.totBusLat 76467385000 # Total cycles spent in databus access
system.physmem.totBankLat 16701547500 # Total cycles spent in bank access
system.physmem.avgQLat 22666.18 # Average queueing delay per request
system.physmem.avgBankLat 1092.07 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.avgMemAccLat 28758.25 # Average memory access latency
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.avgWrQLen 1.13 # Average write queue length over time
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.readRowHits 15218324 # Number of row buffer hits during reads
system.physmem.writeRowHits 794497 # Number of row buffer hits during writes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes
system.physmem.avgGap 157904.04 # Average gap between requests
system.l2c.replacements 64400 # number of replacements
system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use
system.l2c.total_refs 1903586 # Total number of references to valid blocks.
system.l2c.sampled_refs 129789 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.666775 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.occ_percent::cpu0.inst 0.079056 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.049890 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.045985 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.045144 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784452 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 32561 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7200 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 489769 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 212787 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 30618 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6706 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 481086 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 174591 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1435318 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608032 # number of Writeback hits
system.l2c.Writeback_hits::total 608032 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57883 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 54957 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112840 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 32561 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7200 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 489769 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 270670 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 30618 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6706 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 481086 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 229548 # number of demand (read+write) hits
system.l2c.demand_hits::total 1548158 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 32561 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7200 # number of overall hits
system.l2c.overall_hits::cpu0.inst 489769 # number of overall hits
system.l2c.overall_hits::cpu0.data 270670 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 30618 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6706 # number of overall hits
system.l2c.overall_hits::cpu1.inst 481086 # number of overall hits
system.l2c.overall_hits::cpu1.data 229548 # number of overall hits
system.l2c.overall_hits::total 1548158 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 33 # number of ReadReq misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_misses::cpu0.inst 7790 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6089 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4591 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4629 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23144 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1539 # number of UpgradeReq misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_misses::cpu1.data 1367 # number of UpgradeReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 60956 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 72252 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133208 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 33 # number of demand (read+write) misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_misses::cpu0.inst 7790 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 67045 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4591 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 76881 # number of demand (read+write) misses
system.l2c.demand_misses::total 156352 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 33 # number of overall misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_misses::cpu0.inst 7790 # number of overall misses
system.l2c.overall_misses::cpu0.data 67045 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
system.l2c.overall_misses::cpu1.inst 4591 # number of overall misses
system.l2c.overall_misses::cpu1.data 76881 # number of overall misses
system.l2c.overall_misses::total 156352 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2487500 # number of ReadReq miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 431822000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 351847499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 687000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 262625500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 272693999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1322281498 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 226500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 250500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3197672000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3582071000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6779743000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2487500 # number of demand (read+write) miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_miss_latency::cpu0.inst 431822000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3549519499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 687000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 262625500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3854764999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8102024498 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2487500 # number of overall miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_miss_latency::cpu0.inst 431822000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3549519499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 687000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 262625500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3854764999 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8102024498 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 32594 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 7202 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 497559 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 218876 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 30628 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6706 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 485677 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 179220 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1458462 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 608032 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 608032 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1559 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1380 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 118839 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 127209 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246048 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 32594 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 7202 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 497559 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 337715 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 30628 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6706 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 485677 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 306429 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1704510 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 32594 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 7202 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 497559 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 337715 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 30628 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6706 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 485677 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 306429 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1704510 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001012 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000278 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015656 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.027819 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000326 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009453 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025829 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015869 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987171 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990580 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.988772 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.090909 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.512929 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.567979 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.541390 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001012 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000278 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015656 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.198525 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000326 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.009453 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.250893 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091728 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001012 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000278 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015656 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.198525 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000326 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.009453 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.250893 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091728 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75378.787879 # average ReadReq miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55432.862644 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 57784.118739 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68700 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57204.421695 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58909.915533 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 57132.798911 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 147.173489 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 183.247988 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 164.143152 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.691515 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49577.464984 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50895.914660 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75378.787879 # average overall miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 55432.862644 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52942.344679 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68700 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 57204.421695 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 50139.371223 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51819.129260 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75378.787879 # average overall miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 55432.862644 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52942.344679 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68700 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 57204.421695 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 50139.371223 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51819.129260 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.writebacks::writebacks 59161 # number of writebacks
system.l2c.writebacks::total 59161 # number of writebacks
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.data 19 # number of ReadReq MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 33 # number of ReadReq MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 7781 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6049 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 4586 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4610 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23071 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1539 # number of UpgradeReq MSHR misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1367 # number of UpgradeReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.UpgradeReq_mshr_misses::total 2906 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 60956 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 72252 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133208 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 33 # number of demand (read+write) MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 7781 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 67005 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 4586 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 76862 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156279 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 33 # number of overall MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 7781 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 67005 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 4586 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 76862 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156279 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2076782 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334596257 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 274511433 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 562510 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 205256044 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 214462572 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1031558849 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15391539 # number of UpgradeReq MSHR miss cycles
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13671367 # number of UpgradeReq MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.UpgradeReq_mshr_miss_latency::total 29062906 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2437522339 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2681989578 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5119511917 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2076782 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 334596257 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2712033772 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 562510 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 205256044 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2896452150 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6151070766 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2076782 # number of overall MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 334596257 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2712033772 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 562510 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 205256044 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2896452150 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6151070766 # number of overall MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84192530267 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82770547004 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166968129601 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10488033620 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13257430317 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 23745463937 # number of WriteReq MSHR uncacheable cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94680563887 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96027977321 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190713593538 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027637 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025723 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015819 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987171 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990580 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.988772 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.512929 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567979 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541390 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091686 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091686 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average ReadReq mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45381.291618 # average ReadReq mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46521.165293 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44712.359629 # average ReadReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39988.226573 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37119.935476 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38432.465895 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.branchPred.lookups 7600384 # Number of BP lookups
system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dtb.read_hits 26040938 # DTB read hits
system.cpu0.dtb.read_misses 40555 # DTB read misses
system.cpu0.dtb.write_hits 5901951 # DTB write hits
system.cpu0.dtb.write_misses 9434 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 26081493 # DTB read accesses
system.cpu0.dtb.write_accesses 5911385 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dtb.hits 31942889 # DTB hits
system.cpu0.dtb.misses 49989 # DTB misses
system.cpu0.dtb.accesses 31992878 # DTB accesses
system.cpu0.itb.inst_hits 6096045 # ITB inst hits
system.cpu0.itb.inst_misses 7428 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses
system.cpu0.itb.hits 6096045 # DTB hits
system.cpu0.itb.misses 7428 # DTB misses
system.cpu0.itb.accesses 6103473 # DTB accesses
system.cpu0.numCycles 239139269 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued
system.cpu0.iq.rate 0.263933 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iew.exec_nop 116824 # number of nop insts executed
system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed
system.cpu0.iew.exec_branches 6012851 # Number of branches executed
system.cpu0.iew.exec_stores 6171754 # Number of stores executed
system.cpu0.iew.exec_rate 0.259024 # Inst execution rate
system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 24268667 # num instructions producing a value
system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6906334 9.09% 90.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2042059 2.69% 93.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1137631 1.50% 94.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1039888 1.37% 95.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 547173 0.72% 96.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 697067 0.92% 97.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 371357 0.49% 98.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1474476 1.94% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.commit.committed_per_cycle::total 75970705 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 31216883 # Number of instructions committed
system.cpu0.commit.committedOps 39876471 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.commit.refs 13959740 # Number of memory references committed
system.cpu0.commit.loads 8060834 # Number of loads committed
system.cpu0.commit.membars 211745 # Number of memory barriers committed
system.cpu0.commit.branches 5194005 # Number of branches committed
system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 35234084 # Number of committed integer instructions.
system.cpu0.commit.function_calls 512673 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1474476 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.rob.rob_reads 123727475 # The number of ROB reads
system.cpu0.rob.rob_writes 102131366 # The number of ROB writes
system.cpu0.timesIdled 883402 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 161489905 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2289692501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 31137553 # Number of Instructions Simulated
system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated
system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.130207 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.130207 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 280388173 # number of integer regfile reads
system.cpu0.int_regfile_writes 45343219 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22835 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19826 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15490012 # number of misc regfile reads
system.cpu0.misc_regfile_writes 428542 # number of misc regfile writes
system.cpu0.icache.replacements 983837 # number of replacements
system.cpu0.icache.tagsinuse 511.608434 # Cycle average of tags in use
system.cpu0.icache.total_refs 11044105 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 984349 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 11.219705 # Average number of references to valid blocks.
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit.
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.icache.occ_blocks::cpu0.inst 356.557711 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 155.050723 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.696402 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.302833 # Average percentage of cache occupancy
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.icache.ReadReq_hits::cpu0.inst 5554519 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5489586 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 11044105 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5554519 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5489586 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 11044105 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5554519 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5489586 # number of overall hits
system.cpu0.icache.overall_hits::total 11044105 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 539384 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 525964 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 539384 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 525964 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 539384 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 525964 # number of overall misses
system.cpu0.icache.overall_misses::total 1065348 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306834994 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6986624997 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14293459991 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7306834994 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6986624997 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14293459991 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7306834994 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6986624997 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14293459991 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6093903 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 6015550 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 12109453 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6093903 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 6015550 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 12109453 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6093903 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 6015550 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 12109453 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088512 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087434 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.087977 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088512 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087434 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.087977 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088512 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087434 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.087977 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13546.629107 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13283.466163 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.705143 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13416.705143 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13416.705143 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5066 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 940 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 333 # number of cycles access was blocked
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.213213 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 940 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41253 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39724 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 80977 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 41253 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39724 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 80977 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 41253 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39724 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 80977 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498131 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486240 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 984371 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 498131 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 486240 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 984371 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 498131 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 486240 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 984371 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5959731494 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5688421497 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648152991 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5959731494 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5688421497 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11648152991 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5959731494 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5688421497 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11648152991 # number of overall MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081289 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.081289 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.081289 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11833.092392 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11833.092392 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11833.092392 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.replacements 643632 # number of replacements
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.total_refs 21539031 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 644144 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.438223 # Average number of references to valid blocks.
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit.
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.occ_blocks::cpu0.data 318.855973 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 193.136748 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.622766 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.377220 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 7102728 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6679613 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13782341 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3764279 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3497770 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 7262049 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125347 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 118612 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243959 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127468 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120149 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247617 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10867007 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10177383 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21044390 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10867007 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10177383 # number of overall hits
system.cpu0.dcache.overall_hits::total 21044390 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 432162 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 317706 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 749868 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1404882 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1555981 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2960863 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6865 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6770 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13635 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1837044 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1873687 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3710731 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1837044 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1873687 # number of overall misses
system.cpu0.dcache.overall_misses::total 3710731 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6446831500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4972718500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11419550000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53651379846 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60828015793 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114479395639 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92928500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94557500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 187486000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 77000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 60098211346 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 65800734293 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125898945639 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 60098211346 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 65800734293 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125898945639 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7534890 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6997319 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14532209 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5169161 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5053751 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10222912 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132212 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125382 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 257594 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127473 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120155 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247628 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12704051 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12051070 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24755121 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12704051 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12051070 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24755121 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057355 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045404 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051600 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271781 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.307886 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289630 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051924 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053995 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052932 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000039 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.144603 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155479 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149898 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.144603 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155479 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149898 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14917.626955 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15651.950231 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15228.746926 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38189.242830 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39093.032494 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38664.198796 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13536.562272 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.134417 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13750.348368 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15400 # average StoreCondReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14090.909091 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32714.628145 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35118.317143 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33928.340707 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32714.628145 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35118.317143 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33928.340707 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 34713 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 17159 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3563 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 258 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.742633 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 66.507752 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.writebacks::writebacks 608032 # number of writebacks
system.cpu0.dcache.writebacks::total 608032 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 219382 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 144497 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 363879 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1284538 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1427444 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2711982 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 707 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1503920 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1571941 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3075861 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1503920 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1571941 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3075861 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212780 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 173209 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 385989 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 120344 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 128537 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 248881 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6150 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6063 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 333124 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 301746 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 634870 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 333124 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 301746 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 634870 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2896058500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2345588000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5241646500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4040706484 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4421917442 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462623926 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72222000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74035000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146257000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 67000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6936764984 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6767505442 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13704270426 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6936764984 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6767505442 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13704270426 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91949852000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90406740000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356592000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14910322570 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18705155021 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33615477591 # number of WriteReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106860174570 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109111895021 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215972069591 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028239 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024754 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026561 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023281 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025434 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024345 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046516 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048356 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025646 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025646 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13610.576652 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13541.952208 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13579.782066 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33576.301968 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34401.903281 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.691752 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11743.414634 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12210.951674 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11975.517891 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.branchPred.lookups 7054454 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.dtb.read_hits 25326740 # DTB read hits
system.cpu1.dtb.read_misses 36422 # DTB read misses
system.cpu1.dtb.write_hits 5812086 # DTB write hits
system.cpu1.dtb.write_misses 9253 # DTB write misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25363162 # DTB read accesses
system.cpu1.dtb.write_accesses 5821339 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.dtb.hits 31138826 # DTB hits
system.cpu1.dtb.misses 45675 # DTB misses
system.cpu1.dtb.accesses 31184501 # DTB accesses
system.cpu1.itb.inst_hits 6017589 # ITB inst hits
system.cpu1.itb.inst_misses 6780 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses
system.cpu1.itb.hits 6017589 # DTB hits
system.cpu1.itb.misses 6780 # DTB misses
system.cpu1.itb.accesses 6024369 # DTB accesses
system.cpu1.numCycles 234207757 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued
system.cpu1.iq.rate 0.259905 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iew.exec_nop 105357 # number of nop insts executed
system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5535621 # Number of branches executed
system.cpu1.iew.exec_stores 6054470 # Number of stores executed
system.cpu1.iew.exec_rate 0.254039 # Inst execution rate
system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 22806182 # num instructions producing a value
system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 29243924 # Number of instructions committed
system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.commit.refs 13428354 # Number of memory references committed
system.cpu1.commit.loads 7594566 # Number of loads committed
system.cpu1.commit.membars 191899 # Number of memory barriers committed
system.cpu1.commit.branches 4767702 # Number of branches committed
system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions.
system.cpu1.commit.function_calls 478655 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.rob.rob_reads 119446868 # The number of ROB reads
system.cpu1.rob.rob_writes 98500710 # The number of ROB writes
system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 29172873 # Number of Instructions Simulated
system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated
system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads
system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes
system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads
system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink