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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

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Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87713500 # Number of ticks simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
host_inst_rate 1664146 # Simulator instruction rate (inst/s)
host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 215483439 # Simulator tick rate (ticks/s)
host_mem_usage 1139232 # Number of bytes of host memory used
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
host_seconds 0.41 # Real time elapsed on the host
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
sim_insts 677340 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 677340 # Number of ops (including micro ops) simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.physmem.bytes_read 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 559 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175428 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.committedInsts 175339 # Number of instructions committed
system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 28825 # number of instructions that are conditional controls
system.cpu0.num_int_insts 120388 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 349308 # number of times the integer registers were read
system.cpu0.num_int_register_writes 121996 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 82398 # number of memory refs
system.cpu0.num_load_insts 54592 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 175428 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use
system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits
system.cpu0.icache.overall_hits::total 174934 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use
system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits
system.cpu0.dcache.overall_hits::total 82009 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks
system.cpu0.dcache.writebacks::total 6 # number of writebacks
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 173308 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.committedInsts 167398 # Number of instructions committed
system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
system.cpu1.num_int_insts 109926 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 53394 # number of memory refs
system.cpu1.num_load_insts 40652 # Number of load instructions
system.cpu1.num_store_insts 12742 # Number of store instructions
system.cpu1.num_idle_cycles 7886.574443 # Number of idle cycles
system.cpu1.num_busy_cycles 165421.425557 # Number of busy cycles
system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles
system.cpu1.icache.replacements 278 # number of replacements
system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use
system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
system.cpu1.icache.overall_hits::total 167072 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
system.cpu1.icache.overall_misses::total 358 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
system.cpu1.icache.cache_copies 0 # number of cache copies performed
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use
system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits
system.cpu1.dcache.overall_hits::total 53031 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses
system.cpu1.dcache.overall_misses::total 282 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu1.dcache.writebacks::total 1 # number of writebacks
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
test: Update stats for python object iteration. Small changes in tests with data races due to new object creation order.
2010-08-17 14:14:03 +02:00
system.cpu2.numCycles 173308 # number of cpu cycles simulated
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.committedInsts 167334 # Number of instructions committed
system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.num_int_insts 113333 # number of integer instructions
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.num_fp_insts 0 # number of float instructions
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.num_mem_refs 58537 # number of memory refs
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.num_load_insts 42362 # Number of load instructions
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu2.num_store_insts 16175 # Number of store instructions
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.num_idle_cycles 7949.801380 # Number of idle cycles
system.cpu2.num_busy_cycles 165358.198620 # Number of busy cycles
system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles
system.cpu2.icache.replacements 278 # number of replacements
system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use
system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.icache.occ_blocks::cpu2.inst 74.775474 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.146046 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.146046 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
system.cpu2.icache.overall_hits::total 167008 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
system.cpu2.icache.overall_misses::total 358 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 2 # number of replacements
system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use
system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits
system.cpu2.dcache.overall_hits::total 58190 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses
system.cpu2.dcache.overall_misses::total 271 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu2.dcache.writebacks::total 1 # number of writebacks
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173307 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.committedInsts 167269 # Number of instructions committed
system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
system.cpu3.num_int_insts 111554 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 55900 # number of memory refs
system.cpu3.num_load_insts 41466 # Number of load instructions
system.cpu3.num_store_insts 14434 # Number of store instructions
system.cpu3.num_idle_cycles 8013.969997 # Number of idle cycles
system.cpu3.num_busy_cycles 165293.030003 # Number of busy cycles
system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles
system.cpu3.icache.replacements 279 # number of replacements
system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use
system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.icache.occ_blocks::cpu3.inst 72.869097 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.142322 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.142322 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
system.cpu3.icache.overall_hits::total 166942 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
system.cpu3.icache.cache_copies 0 # number of cache copies performed
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 2 # number of replacements
system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use
system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits
system.cpu3.dcache.overall_hits::total 55559 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses
system.cpu3.dcache.overall_misses::total 261 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu3.dcache.writebacks::total 1 # number of writebacks
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 371.980910 # Cycle average of tags in use
system.l2c.total_refs 1223 # Total number of references to valid blocks.
system.l2c.sampled_refs 426 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.870892 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.Writeback_hits::total 9 # number of Writeback hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.demand_hits::total 1226 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.overall_hits::total 1226 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.overall_misses::total 559 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses)
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink