gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000124                       # Number of seconds simulated
sim_ticks                                   123936000                       # Number of ticks simulated
final_tick                                  123936000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 188054                       # Simulator instruction rate (inst/s)
host_op_rate                                   188053                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               20091950                       # Simulator tick rate (ticks/s)
host_mem_usage                                 268856                       # Number of bytes of host memory used
host_seconds                                     6.17                       # Real time elapsed on the host
sim_insts                                     1159992                       # Number of instructions simulated
sim_ops                                       1159992                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst            24064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::total                45376                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        24064                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          640                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           31296                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               376                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                89                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                21                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   709                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           194164730                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            87787245                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            45959205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            10844307                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             7229538                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7745933                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             5163956                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7229538                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               366124451                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      194164730                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       45959205                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        7229538                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        5163956                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          252517428                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          194164730                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           87787245                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           45959205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           10844307                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            7229538                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7745933                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            5163956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7229538                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              366124451                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           709                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         709                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    45376                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     45376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  44                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  62                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  69                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 69                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 45                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       123701000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     709                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       430                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       203                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          169                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      251.076923                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     166.451829                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     245.101340                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             63     37.28%     37.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           39     23.08%     60.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           28     16.57%     76.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           13      7.69%     84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            8      4.73%     89.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            8      4.73%     94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      1.78%     95.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      0.59%     96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      3.55%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            169                       # Bytes accessed per row activation
system.physmem.totQLat                        6766000                       # Total ticks spent queuing
system.physmem.totMemAccLat                  20059750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3545000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9543.02                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28293.02                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         366.12                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      366.12                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.86                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.86                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        528                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       174472.50                       # Average gap between requests
system.physmem.pageHitRate                      74.47                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     831600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     453750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2925000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                7628400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               49377960                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               26918250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 88134960                       # Total energy per rank (pJ)
system.physmem_0.averagePower              752.944352                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE       47288500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         3900000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        68692500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     408240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     222750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2184000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                7628400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               42901335                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               32591250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 85935975                       # Total energy per rank (pJ)
system.physmem_1.averagePower              734.244489                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE       54352750                       # Time in different power states
system.physmem_1.memoryStateTime::REF         3900000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        59251250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups                  98531                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            94014                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1575                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               95788                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                   1142                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups          95788                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits             88519                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses            7269                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted         1054                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                          247873                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             23367                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        581451                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      98531                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             89661                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       193123                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3449                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        66                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         2208                       # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                     7997                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  861                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples            220500                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.636966                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.261585                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   33425     15.16%     15.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   91538     41.51%     56.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     694      0.31%     56.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1015      0.46%     57.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     497      0.23%     57.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   87060     39.48%     97.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     731      0.33%     97.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     514      0.23%     97.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    5026      2.28%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              220500                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.397506                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.345762                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17843                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                18591                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   181526                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  816                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1724                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                563984                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1724                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18505                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1935                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         15328                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   181668                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1340                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                558880                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   869                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             382489                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1113780                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          841332                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups                2                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps               363591                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   18898                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1094                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1121                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     5347                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              178321                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              90063                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            86944                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           86670                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    466208                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1118                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   462266                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              112                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          16406                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        13115                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           559                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       220500                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.096444                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.103875                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              36239     16.43%     16.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4459      2.02%     18.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              88275     40.03%     58.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              87972     39.90%     98.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1699      0.77%     99.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                988      0.45%     99.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                572      0.26%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                195      0.09%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                101      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         220500                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                    126     38.77%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     38.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    78     24.00%     62.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  121     37.23%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               195215     42.23%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              177740     38.45%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              89311     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                462266                       # Type of FU issued
system.cpu0.iq.rate                          1.864931                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        325                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000703                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1145469                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           483779                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       459725                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                462591                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           86430                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2936                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses           13                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           53                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1864                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           11                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1724                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1933                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             554898                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              123                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               178321                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               90063                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts              1001                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            53                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           229                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1693                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1922                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               460834                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               177384                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1432                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        87572                       # number of nop insts executed
system.cpu0.iew.exec_refs                      266499                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   91565                       # Number of branches executed
system.cpu0.iew.exec_stores                     89115                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.859154                       # Inst execution rate
system.cpu0.iew.wb_sent                        460184                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       459725                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   272583                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   276120                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.854680                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.987190                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          17076                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1575                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       217161                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.476218                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.140669                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        36214     16.68%     16.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        90367     41.61%     58.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2049      0.94%     59.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          624      0.29%     59.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          510      0.23%     59.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        86212     39.70%     99.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          445      0.20%     99.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          289      0.13%     99.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          451      0.21%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       217161                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              537738                       # Number of instructions committed
system.cpu0.commit.committedOps                537738                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        263584                       # Number of memory references committed
system.cpu0.commit.loads                       175385                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     90086                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   361922                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        86818     16.15%     16.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          187252     34.82%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         175469     32.63%     83.60% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         88199     16.40%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           537738                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  451                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      770363                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1113018                       # The number of ROB writes
system.cpu0.timesIdled                            321                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          27373                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     450836                       # Number of Instructions Simulated
system.cpu0.committedOps                       450836                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.549807                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.549807                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.818819                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.818819                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  823745                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 371341                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 268638                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          142.669467                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             177790                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs          1033.662791                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.669467                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.278651                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.278651                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           716504                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          716504                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data        90267                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          90267                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        87606                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         87606                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           22                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             22                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       177873                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          177873                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       177873                       # number of overall hits
system.cpu0.dcache.overall_hits::total         177873                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          580                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          580                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          551                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          551                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           20                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           20                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1131                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1131                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1131                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1131                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     15004000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     15004000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35761990                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     35761990                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       487500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       487500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     50765990                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     50765990                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     50765990                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     50765990                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        90847                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        90847                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        88157                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        88157                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       179004                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       179004                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       179004                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       179004                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006384                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006384                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006250                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006250                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006318                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006318                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006318                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006318                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        24375                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total        24375                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          832                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.818182                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          378                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          378                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          383                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          383                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          761                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          761                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          761                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          761                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          202                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          168                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          168                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          370                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          370                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          370                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          370                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6835500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6835500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8076500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8076500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       467500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       467500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     14912000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     14912000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     14912000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     14912000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002224                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002224                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001906                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001906                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002067                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002067                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002067                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002067                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33839.108911                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33839.108911                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48074.404762                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48074.404762                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        23375                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        23375                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40302.702703                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40302.702703                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703                       # average overall mshr miss latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements              413                       # number of replacements
system.cpu0.icache.tags.tagsinuse          250.106503                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               7058                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              712                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.912921                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   250.106503                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.488489                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.488489                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           41                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          190                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.583984                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             8709                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            8709                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst         7058                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           7058                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         7058                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            7058                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         7058                       # number of overall hits
system.cpu0.icache.overall_hits::total           7058                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          939                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          939                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          939                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           939                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          939                       # number of overall misses
system.cpu0.icache.overall_misses::total          939                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     44243500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     44243500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     44243500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     44243500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     44243500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     44243500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         7997                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         7997                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         7997                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         7997                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         7997                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         7997                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117419                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.117419                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117419                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.117419                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117419                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.117419                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 47117.678381                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 47117.678381                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          117                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.250000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          413                       # number of writebacks
system.cpu0.icache.writebacks::total              413                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          226                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          226                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          226                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          226                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          226                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          226                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          713                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          713                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          713                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          713                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          713                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          713                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     34164500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     34164500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     34164500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     34164500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     34164500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     34164500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.089158                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.089158                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.089158                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                  73042                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            65659                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             2238                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               64943                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                   1989                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups          64943                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits             55241                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses            9702                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted         1128                       # Number of mispredicted indirect branches.
system.cpu1.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                          192502                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             33710                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        406560                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      73042                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             57230                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       148689                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4633                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1669                       # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                    22180                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  918                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            186413                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             2.180964                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.381342                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   54977     29.49%     29.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   63721     34.18%     63.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5493      2.95%     66.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3499      1.88%     68.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     651      0.35%     68.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   47493     25.48%     94.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                     995      0.53%     94.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                    1355      0.73%     95.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    8229      4.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              186413                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.379435                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       2.111978                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   22012                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                48189                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   110683                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3203                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2316                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                375249                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2316                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   23003                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  21046                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13565                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   110960                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                15513                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                369118                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 12808                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    18                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             260404                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               717496                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          555302                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups               32                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps               234261                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   26143                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1622                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1759                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    20875                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads              105786                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              51568                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            49714                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           45358                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    305985                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               5880                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   304555                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               84                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          23105                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        18122                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved          1124                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       186413                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.633765                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.368784                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              59464     31.90%     31.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              19554     10.49%     42.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              50315     26.99%     69.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              50093     26.87%     96.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3572      1.92%     98.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1698      0.91%     99.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6               1008      0.54%     99.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                406      0.22%     99.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                303      0.16%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         186413                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                    182     38.89%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     38.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    58     12.39%     51.28% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  228     48.72%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               145063     47.63%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.63% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead              108861     35.74%     83.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              50631     16.62%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                304555                       # Type of FU issued
system.cpu1.iq.rate                          1.582087                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        468                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001537                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            796075                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           334945                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       300973                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                305023                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           45252                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         4194                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses           25                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         2536                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2316                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   6366                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             362764                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              272                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts               105786                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               51568                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1528                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         2397                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                2840                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               302276                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts               104291                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             2279                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        50899                       # number of nop insts executed
system.cpu1.iew.exec_refs                      154635                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   61121                       # Number of branches executed
system.cpu1.iew.exec_stores                     50344                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.570249                       # Inst execution rate
system.cpu1.iew.wb_sent                        301460                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       300973                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   172395                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   179828                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.563480                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.958666                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          24140                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           4756                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             2238                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       181815                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.862272                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.110451                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        63682     35.03%     35.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        57506     31.63%     66.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5445      2.99%     69.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         5412      2.98%     72.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1312      0.72%     73.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        45472     25.01%     98.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          770      0.42%     98.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          999      0.55%     99.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1217      0.67%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       181815                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              338589                       # Number of instructions committed
system.cpu1.commit.committedOps                338589                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        150624                       # Number of memory references committed
system.cpu1.commit.loads                       101592                       # Number of loads committed
system.cpu1.commit.membars                       4041                       # Number of memory barriers committed
system.cpu1.commit.branches                     59040                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   231783                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        49829     14.72%     14.72% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          134095     39.60%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.32% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead         105633     31.20%     85.52% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         49032     14.48%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           338589                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1217                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      542741                       # The number of ROB reads
system.cpu1.rob.rob_writes                     730091                       # The number of ROB writes
system.cpu1.timesIdled                            236                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           6089                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       47433                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     284719                       # Number of Instructions Simulated
system.cpu1.committedOps                       284719                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.676112                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.676112                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.479044                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.479044                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  527704                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 245054                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 156484                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           26.869792                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              56025                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1931.896552                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.869792                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.052480                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.052480                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           432447                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          432447                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data        58508                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          58508                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        48814                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         48814                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data       107322                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total          107322                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data       107322                       # number of overall hits
system.cpu1.dcache.overall_hits::total         107322                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          507                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          507                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          149                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          149                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           58                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          656                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           656                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          656                       # number of overall misses
system.cpu1.dcache.overall_misses::total          656                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4815500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      4815500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3532500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3532500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       364000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       364000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      8348000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      8348000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      8348000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      8348000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        59015                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        59015                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        48963                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        48963                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data       107978                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total       107978                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data       107978                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total       107978                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008591                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008591                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003043                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003043                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.840580                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.840580                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006075                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006075                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006075                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006075                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data  9498.027613                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total  9498.027613                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6275.862069                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  6275.862069                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          344                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          344                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           43                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           43                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          387                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          387                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          387                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          387                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          163                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           58                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          269                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          269                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1494500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1494500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1455500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1455500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       306000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       306000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2950000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2950000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2950000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2950000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002762                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002762                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002165                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002165                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.840580                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.840580                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002491                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002491                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002491                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002491                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9168.711656                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9168.711656                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  5275.862069                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  5275.862069                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751                       # average overall mshr miss latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements              556                       # number of replacements
system.cpu1.icache.tags.tagsinuse           97.374754                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              21335                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              687                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            31.055313                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.374754                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190185                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.190185                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          131                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.255859                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            22867                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           22867                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst        21335                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          21335                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        21335                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           21335                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        21335                       # number of overall hits
system.cpu1.icache.overall_hits::total          21335                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          845                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          845                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          845                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           845                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          845                       # number of overall misses
system.cpu1.icache.overall_misses::total          845                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     18952000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     18952000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     18952000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     18952000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     18952000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     18952000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        22180                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        22180                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        22180                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        22180                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        22180                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        22180                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038097                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.038097                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038097                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.038097                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038097                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.038097                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 22428.402367                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 22428.402367                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          141                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    35.250000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks          556                       # number of writebacks
system.cpu1.icache.writebacks::total              556                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          158                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total          158                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst          158                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total          158                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst          158                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total          158                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          687                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          687                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          687                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          687                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          687                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          687                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     14723000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     14723000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     14723000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     14723000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     14723000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     14723000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030974                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030974                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030974                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806                       # average overall mshr miss latency
system.cpu2.branchPred.lookups                  66096                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            57926                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             2486                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               57464                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                   2115                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups          57464                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits             46751                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           10713                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted         1349                       # Number of mispredicted indirect branches.
system.cpu2.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
system.cpu2.numCycles                          192112                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             39817                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        356778                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      66096                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             48866                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       146191                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   5129                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1920                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles            3                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                    28579                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  972                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            190509                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.872762                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.344982                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   72004     37.80%     37.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   58377     30.64%     68.44% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8422      4.42%     72.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3406      1.79%     74.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     670      0.35%     75.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   36267     19.04%     94.04% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1053      0.55%     94.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                    1474      0.77%     95.36% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    8836      4.64%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              190509                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.344049                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.857135                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   22990                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                70899                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    89451                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 4595                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2564                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                324452                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2564                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   24019                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  34614                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13407                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    89996                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                25899                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                317685                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 22128                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    16                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             221990                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               601950                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          469192                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               40                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps               192480                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   29510                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1686                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1819                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    31415                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               86703                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              40578                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            41384                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           34173                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    258235                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8782                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   258833                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               83                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          25653                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        20039                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved          1265                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       190509                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.358639                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.384430                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              76931     40.38%     40.38% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              28046     14.72%     55.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              39341     20.65%     75.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              39028     20.49%     96.24% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3604      1.89%     98.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1759      0.92%     99.06% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6               1073      0.56%     99.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                444      0.23%     99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                283      0.15%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         190509                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                    204     42.15%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     42.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    51     10.54%     52.69% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  229     47.31%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               126867     49.02%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.02% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               92395     35.70%     84.71% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              39571     15.29%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                258833                       # Type of FU issued
system.cpu2.iq.rate                          1.347303                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        484                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001870                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            708742                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           292626                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       254835                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                80                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                259317                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           34129                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         4624                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses           33                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         2677                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2564                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   9290                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             309688                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              288                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                86703                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               40578                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1561                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    34                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            36                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         2684                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                3127                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               256258                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                85016                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             2575                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        42671                       # number of nop insts executed
system.cpu2.iew.exec_refs                      124288                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   53042                       # Number of branches executed
system.cpu2.iew.exec_stores                     39272                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.333899                       # Inst execution rate
system.cpu2.iew.wb_sent                        255341                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       254835                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   142252                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   149928                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.326492                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.948802                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          26847                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7517                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             2486                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       185379                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.525604                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.006612                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        83888     45.25%     45.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        49216     26.55%     71.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5545      2.99%     74.79% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         8151      4.40%     79.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1274      0.69%     79.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        34338     18.52%     98.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          700      0.38%     98.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1066      0.58%     99.35% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1201      0.65%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       185379                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              282815                       # Number of instructions committed
system.cpu2.commit.committedOps                282815                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        119980                       # Number of memory references committed
system.cpu2.commit.loads                        82079                       # Number of loads committed
system.cpu2.commit.membars                       6800                       # Number of memory barriers committed
system.cpu2.commit.branches                     50664                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   192763                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        41451     14.66%     14.66% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          114584     40.52%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.17% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          88879     31.43%     86.60% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         37901     13.40%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           282815                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1201                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      493254                       # The number of ROB reads
system.cpu2.rob.rob_writes                     624500                       # The number of ROB writes
system.cpu2.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1603                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       47823                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     234564                       # Number of Instructions Simulated
system.cpu2.committedOps                       234564                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.819017                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.819017                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.220975                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.220975                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  437605                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 204427                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 126238                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           26.114184                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              45075                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1502.500000                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.114184                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051004                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.051004                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           355312                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          355312                       # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data        50364                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          50364                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        37691                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         37691                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        88055                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           88055                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        88055                       # number of overall hits
system.cpu2.dcache.overall_hits::total          88055                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          498                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          498                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          637                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           637                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          637                       # number of overall misses
system.cpu2.dcache.overall_misses::total          637                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3990000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      3990000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2835500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2835500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       366500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       366500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      6825500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      6825500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      6825500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      6825500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        50862                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        50862                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        37830                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        37830                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        88692                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        88692                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        88692                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        88692                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009791                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.009791                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003674                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003674                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007182                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.007182                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007182                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.007182                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  8012.048193                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total  8012.048193                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  6318.965517                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  6318.965517                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          331                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          331                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           34                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          365                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          365                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          365                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          365                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          167                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          272                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          272                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1193000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1193000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1388000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1388000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       308500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       308500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2581000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2581000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2581000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2581000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003283                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003283                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002776                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002776                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003067                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003067                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003067                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003067                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  7143.712575                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  7143.712575                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  5318.965517                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  5318.965517                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9488.970588                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9488.970588                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9488.970588                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9488.970588                       # average overall mshr miss latency
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements              578                       # number of replacements
system.cpu2.icache.tags.tagsinuse           95.404705                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              27742                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              710                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            39.073239                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    95.404705                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.186337                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.186337                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          132                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.257812                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            29289                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           29289                       # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst        27742                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          27742                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        27742                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           27742                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        27742                       # number of overall hits
system.cpu2.icache.overall_hits::total          27742                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          837                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          837                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          837                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           837                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          837                       # number of overall misses
system.cpu2.icache.overall_misses::total          837                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12852000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     12852000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     12852000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     12852000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     12852000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     12852000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        28579                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        28579                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        28579                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        28579                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        28579                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        28579                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.029287                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.029287                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.029287                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.029287                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.029287                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.029287                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15354.838710                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15354.838710                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           69                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           23                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks          578                       # number of writebacks
system.cpu2.icache.writebacks::total              578                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          127                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total          127                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst          127                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total          127                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst          127                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total          127                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          710                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          710                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          710                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          710                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          710                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          710                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10853000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     10853000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10853000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     10853000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10853000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     10853000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.024843                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.024843                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.024843                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493                       # average overall mshr miss latency
system.cpu3.branchPred.lookups                  58058                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            50256                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             2406                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               50211                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                   1984                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups          50211                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits             39339                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses           10872                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted         1290                       # Number of mispredicted indirect branches.
system.cpu3.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
system.cpu3.numCycles                          191755                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             44345                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        305380                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      58058                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             41323                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       141573                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4965                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1720                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    32940                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  916                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            190133                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.606139                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.261267                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   84706     44.55%     44.55% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   53051     27.90%     72.45% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                   10689      5.62%     78.07% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3433      1.81%     79.88% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     679      0.36%     80.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   26352     13.86%     94.10% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1085      0.57%     94.67% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                    1438      0.76%     95.42% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    8700      4.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              190133                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.302772                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.592553                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   22846                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                89002                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    70141                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 5652                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2482                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                273868                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2482                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   23847                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  45287                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         13384                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    70737                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                34386                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                267452                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 29592                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.RenamedOperands             184677                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               492576                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          387264                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups               20                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps               155405                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   29272                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1682                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1811                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    39856                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               69050                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              30771                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            33750                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           24332                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    213083                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded              11008                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   216315                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               53                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          25213                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        19048                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved          1289                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       190133                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.137704                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.357547                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              89784     47.22%     47.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              34463     18.13%     65.35% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              29348     15.44%     80.78% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              29336     15.43%     96.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3681      1.94%     98.15% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1744      0.92%     99.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6               1040      0.55%     99.61% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                432      0.23%     99.84% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                305      0.16%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         190133                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                    189     39.38%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     39.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    53     11.04%     50.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  238     49.58%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               109511     50.63%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.63% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               77010     35.60%     86.23% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              29794     13.77%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                216315                       # Type of FU issued
system.cpu3.iq.rate                          1.128080                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        480                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.002219                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            623296                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           249298                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       212257                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                40                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                216795                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           24283                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         4403                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses           27                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           34                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         2689                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2482                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                  11408                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             259073                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              473                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                69050                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               30771                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1541                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    26                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           490                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         2580                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                3070                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               213662                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                67471                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             2653                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        34982                       # number of nop insts executed
system.cpu3.iew.exec_refs                       96956                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   45328                       # Number of branches executed
system.cpu3.iew.exec_stores                     29485                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.114245                       # Inst execution rate
system.cpu3.iew.wb_sent                        212766                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       212257                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   115033                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   122695                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.106918                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.937552                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          26335                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           9719                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             2406                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       185183                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.256660                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.878907                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        99076     53.50%     53.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        41559     22.44%     75.94% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5388      2.91%     78.85% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3        10319      5.57%     84.43% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1252      0.68%     85.10% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        24567     13.27%     98.37% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          787      0.42%     98.79% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1025      0.55%     99.35% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1210      0.65%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       185183                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              232712                       # Number of instructions committed
system.cpu3.commit.committedOps                232712                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         92729                       # Number of memory references committed
system.cpu3.commit.loads                        64647                       # Number of loads committed
system.cpu3.commit.membars                       9005                       # Number of memory barriers committed
system.cpu3.commit.branches                     43044                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   157897                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        33834     14.54%     14.54% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu           97144     41.74%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.28% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          73652     31.65%     87.93% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         28082     12.07%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           232712                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1210                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      442434                       # The number of ROB reads
system.cpu3.rob.rob_writes                     523106                       # The number of ROB writes
system.cpu3.timesIdled                            214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1622                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       48179                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     189873                       # Number of Instructions Simulated
system.cpu3.committedOps                       189873                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.009912                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.009912                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.990185                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.990185                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  355771                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 167240                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  98845                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           24.519752                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              35385                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1179.500000                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.519752                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047890                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.047890                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           285185                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          285185                       # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data        42713                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          42713                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        27877                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         27877                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           16                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        70590                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           70590                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        70590                       # number of overall hits
system.cpu3.dcache.overall_hits::total          70590                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          439                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          439                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          137                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          137                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           52                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          576                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           576                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          576                       # number of overall misses
system.cpu3.dcache.overall_misses::total          576                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3185500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      3185500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2743000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2743000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       334000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       334000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      5928500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      5928500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      5928500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      5928500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        43152                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        43152                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        28014                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        28014                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        71166                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        71166                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        71166                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        71166                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010173                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.010173                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004890                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.004890                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.764706                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.764706                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008094                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.008094                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008094                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.008094                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  7256.264237                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total  7256.264237                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6423.076923                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  6423.076923                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          281                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          281                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          314                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          314                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          314                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          314                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          158                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1084000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1084000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1390500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1390500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       282000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       282000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2474500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2474500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2474500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2474500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003661                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003661                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003712                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003712                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.750000                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003682                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003682                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003682                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003682                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6860.759494                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6860.759494                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13370.192308                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5529.411765                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5529.411765                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9444.656489                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9444.656489                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9444.656489                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9444.656489                       # average overall mshr miss latency
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements              578                       # number of replacements
system.cpu3.icache.tags.tagsinuse           92.680953                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              32101                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              713                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            45.022440                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    92.680953                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.181017                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.181017                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.263672                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            33653                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           33653                       # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst        32101                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          32101                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        32101                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           32101                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        32101                       # number of overall hits
system.cpu3.icache.overall_hits::total          32101                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          839                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          839                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          839                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           839                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          839                       # number of overall misses
system.cpu3.icache.overall_misses::total          839                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     11633500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     11633500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     11633500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     11633500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     11633500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     11633500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        32940                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        32940                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        32940                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        32940                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        32940                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        32940                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.025471                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.025471                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.025471                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.025471                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.025471                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.025471                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13865.911800                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13865.911800                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13865.911800                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13865.911800                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks          578                       # number of writebacks
system.cpu3.icache.writebacks::total              578                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          126                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst          126                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total          126                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst          126                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total          126                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          713                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          713                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          713                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          713                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          713                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          713                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     10107000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     10107000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     10107000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     10107000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     10107000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     10107000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021645                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.021645                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.021645                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14175.315568                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 14175.315568                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 14175.315568                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  567.287206                       # Cycle average of tags in use
system.l2c.tags.total_refs                       3156                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      709                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.451340                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::cpu0.inst      303.185096                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data      145.120224                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       69.165941                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       16.093016                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst        8.947029                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data       10.727803                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        4.254567                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        9.793531                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::cpu0.inst       0.004626                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.002214                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001055                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000246                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000137                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000164                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000065                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000149                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.008656                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          709                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          487                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.010818                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    31781                       # Number of tag accesses
system.l2c.tags.data_accesses                   31781                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          719                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             719                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              24                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              19                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              22                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              23                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  88                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           334                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           594                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           687                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           700                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              2315                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 334                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 594                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 687                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 700                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    2347                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                334                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                594                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                687                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                700                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   2347                       # number of overall hits
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          379                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           93                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           23                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst           13                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             508                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            8                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             89                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               379                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                93                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                21                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   728                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              379                       # number of overall misses
system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               93                       # number of overall misses
system.l2c.overall_misses::cpu1.data               21                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               23                       # number of overall misses
system.l2c.overall_misses::cpu2.data               15                       # number of overall misses
system.l2c.overall_misses::cpu3.inst               13                       # number of overall misses
system.l2c.overall_misses::cpu3.data               14                       # number of overall misses
system.l2c.overall_misses::total                  728                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7826500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      1039500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       940000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       937000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     10743000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     29388500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6947000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      2007500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst      1084500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     39427500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      6119500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       658500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       265000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       181000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      7224000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     29388500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     13946000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      6947000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1698000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      2007500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1205000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst      1084500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        57394500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     29388500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     13946000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      6947000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1698000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      2007500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1205000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst      1084500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       57394500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          719                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          719                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              88                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          713                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          687                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          710                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          713                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2823                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          121                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             713                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             687                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             710                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             713                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                3075                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            713                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            687                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            710                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            713                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               3075                       # number of overall (read+write) accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.531557                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.135371                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.032394                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.018233                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.179950                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.615385                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.214286                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.735537                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.531557                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.135371                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.807692                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.032394                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.576923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.018233                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.236748                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.531557                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.135371                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.807692                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.032394                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.576923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.018233                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.236748                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83260.638298                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78083.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 82007.633588                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77542.216359                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74698.924731                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 87282.608696                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83423.076923                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 77613.188976                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80519.736842                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82312.500000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 88333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        90500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 81168.539326                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 77542.216359                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 82035.294118                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74698.924731                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 80857.142857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 87282.608696                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 80333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 83423.076923                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 79857.142857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78838.598901                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 77542.216359                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 82035.294118                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74698.924731                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 80857.142857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 87282.608696                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 80333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 83423.076923                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 79857.142857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78838.598901                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            9                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          377                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           89                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           14                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           10                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          490                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            8                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           89                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          377                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           89                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           21                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              710                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          377                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           89                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           21                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             710                       # number of overall MSHR misses
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6886500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       909500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       820000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       817000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      9433000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     25557000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5847000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1317000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       764500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     33485500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5359500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       578500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       235000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       161000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      6334000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     25557000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     12246000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      5847000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1488000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      1317000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1055000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       764500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       978000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     49252500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     25557000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     12246000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      5847000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1488000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      1317000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1055000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       764500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       978000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     49252500                       # number of overall MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.173574                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.615385                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.735537                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.807692                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.230894                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.807692                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.230894                       # mshr miss rate for overall accesses
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73260.638298                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68083.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        76450                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68337.755102                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70519.736842                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72312.500000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 78333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        80500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71168.539326                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72035.294118                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        76450                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69857.142857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69369.718310                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72035.294118                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        76450                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69857.142857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69369.718310                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           957                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          248                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                578                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              196                       # Transaction distribution
system.membus.trans_dist::ReadExReq               183                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           578                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   45376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              248                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               957                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     957    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 957                       # Request fanout histogram
system.membus.reqLayer0.occupancy              877500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3778750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         6322                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1727                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3289                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp              3509                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean         2125                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             284                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            284                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              398                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             398                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2823                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          690                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1838                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          602                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1930                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1998                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          378                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2004                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          362                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  9484                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        72000                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        79552                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        82432                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        82624                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 332800                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1032                       # Total snoops (count)
system.toL2Bus.snoopTraffic                     53504                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples             4195                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.291538                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.103863                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1306     31.13%     31.13% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                   1176     28.03%     59.17% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    897     21.38%     80.55% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    816     19.45%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               4195                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            5296980                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              4.3                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           1068997                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            528987                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1032995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            438456                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1069486                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            439965                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1070997                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            415480                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------