2007-03-29 19:51:12 +02:00
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---------- Begin Simulation Statistics ----------
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2010-09-22 08:07:35 +02:00
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sim_seconds 0.202942 # Number of seconds simulated
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sim_ticks 202941992000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-13 03:35:03 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-02-12 23:07:43 +01:00
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host_inst_rate 1927976 # Simulator instruction rate (inst/s)
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host_op_rate 1952939 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2911235123 # Simulator tick rate (ticks/s)
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host_mem_usage 220544 # Number of bytes of host memory used
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host_seconds 69.71 # Real time elapsed on the host
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sim_insts 134398975 # Number of instructions simulated
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sim_ops 136139203 # Number of ops (including micro ops) simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 8970304 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 5584960 # Number of bytes written to this memory
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system.physmem.num_reads 140161 # Number of read requests responded to by this memory
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system.physmem.num_writes 87265 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s)
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2011-06-13 03:35:03 +02:00
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system.cpu.workload.num_syscalls 1946 # Number of system calls
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system.cpu.numCycles 405883984 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-12 23:07:43 +01:00
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system.cpu.committedInsts 134398975 # Number of instructions committed
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system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
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2011-06-13 03:35:03 +02:00
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system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
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system.cpu.num_func_calls 1709332 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
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system.cpu.num_int_insts 115187758 # number of integer instructions
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system.cpu.num_fp_insts 2326977 # number of float instructions
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system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
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2011-12-01 00:57:11 +01:00
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system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written
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2011-06-13 03:35:03 +02:00
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system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
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system.cpu.num_mem_refs 58160249 # number of memory refs
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system.cpu.num_load_insts 37275868 # Number of load instructions
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system.cpu.num_store_insts 20884381 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 405883984 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 184976 # number of replacements
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system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use
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system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits
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system.cpu.icache.overall_hits::total 134366560 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
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system.cpu.icache.overall_misses::total 187024 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
|
2011-06-13 03:35:03 +02:00
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|
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-02-12 23:07:43 +01:00
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|
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
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|
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
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system.cpu.dcache.replacements 146582 # number of replacements
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|
|
|
|
system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
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|
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system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
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|
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system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor
|
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system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy
|
|
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system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy
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|
system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
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system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
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system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
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|
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system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits
|
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system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits
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system.cpu.dcache.overall_hits::total 57944942 # number of overall hits
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|
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
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|
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|
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
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|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
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|
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
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system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
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|
|
system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
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|
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
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system.cpu.dcache.overall_misses::total 150663 # number of overall misses
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|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1709246000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 1709246000 # number of ReadReq miss cycles
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|
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|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5738404000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 5738404000 # number of WriteReq miss cycles
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|
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|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles
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|
system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles
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|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles
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|
|
|
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system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles
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|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses)
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|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses)
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|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 118818 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 120138 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 118818 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 3599 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 3599 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 173973 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 23568 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 197541 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 173973 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 23568 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 197541 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13051 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 25530 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 38581 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 101580 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 101580 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13051 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 127110 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 140161 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13051 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 127110 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 140161 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 678652000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1327560000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2006212000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5282160000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5282160000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 678652000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6609720000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 7288372000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 678652000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6609720000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 7288372000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 118818 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 118818 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 87265 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13051 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 25530 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 38581 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101580 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 101580 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13051 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 127110 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 140161 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13051 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 127110 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 140161 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 522040000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1021200000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1543240000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4063200000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4063200000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 522040000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5084400000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 5606440000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 522040000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-03-29 19:51:12 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
