2011-06-21 04:44:22 +02:00
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000018 # Number of seconds simulated
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2011-07-10 19:56:09 +02:00
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sim_ticks 18201500 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-21 04:44:22 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-01-25 18:19:50 +01:00
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host_inst_rate 29731 # Simulator instruction rate (inst/s)
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host_tick_rate 101330259 # Simulator tick rate (ticks/s)
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host_mem_usage 213072 # Number of bytes of host memory used
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host_seconds 0.18 # Real time elapsed on the host
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2011-06-21 04:44:22 +02:00
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sim_insts 5340 # Number of instructions simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 423 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s)
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2011-06-21 04:44:22 +02:00
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system.cpu.workload.num_syscalls 11 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 36404 # number of cpu cycles simulated
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2011-06-21 04:44:22 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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2011-07-10 19:56:09 +02:00
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system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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2011-06-21 04:44:22 +02:00
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
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2011-07-10 19:56:09 +02:00
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system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6274 # Number of cycles cpu stages are processed.
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system.cpu.activity 17.234370 # Percentage of cycles cpu is active
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2011-06-21 04:44:22 +02:00
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system.cpu.comLoads 716 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1116 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2537 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread)
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2011-06-21 04:44:22 +02:00
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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2011-07-10 19:56:09 +02:00
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system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread)
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2011-06-21 04:44:22 +02:00
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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2011-07-10 19:56:09 +02:00
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system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 1662 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits
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2011-06-21 04:44:22 +02:00
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system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
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2011-07-10 19:56:09 +02:00
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system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
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2011-06-21 04:44:22 +02:00
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system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
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2011-07-10 19:56:09 +02:00
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system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File
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2011-06-21 04:44:22 +02:00
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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2011-07-10 19:56:09 +02:00
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system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic
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2011-06-21 04:44:22 +02:00
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system.cpu.agen_unit.agens 1473 # Number of Address Generations
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2011-07-10 19:56:09 +02:00
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system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3977 # Number of Instructions Executed.
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2011-06-21 04:44:22 +02:00
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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2011-07-10 19:56:09 +02:00
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system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed.
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2011-06-21 04:44:22 +02:00
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system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
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2011-07-10 19:56:09 +02:00
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system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts).
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.replacements 0 # number of replacements
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.total_refs 791 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits
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system.cpu.icache.demand_hits 791 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 791 # number of overall hits
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system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses
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system.cpu.icache.demand_misses 347 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 347 # number of overall misses
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
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2011-06-21 04:44:22 +02:00
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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2011-07-10 19:56:09 +02:00
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system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use
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2011-06-21 04:44:22 +02:00
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system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2011-07-10 19:56:09 +02:00
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system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy
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2011-06-21 04:44:22 +02:00
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system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits
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system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 1049 # number of overall hits
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system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses
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system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 340 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles
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|
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system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
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|
|
system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 423 # number of overall misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency
|
2011-06-21 04:44:22 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
