2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.000010 # Number of seconds simulated
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2011-08-19 22:08:06 +02:00
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sim_ticks 9807000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 16610 # Simulator instruction rate (inst/s)
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host_tick_rate 28382842 # Simulator tick rate (ticks/s)
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host_mem_usage 221852 # Number of bytes of host memory used
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host_seconds 0.35 # Real time elapsed on the host
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2011-03-18 01:20:22 +01:00
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sim_insts 5739 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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2011-08-19 22:08:06 +02:00
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system.cpu.numCycles 19615 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 2510 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 1858 # Number of conditional branches predicted
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target.
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions.
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.icacheStallCycles 6260 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 12668 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2510 # Number of branches that fetch encountered
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.Cycles 2827 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1646 # Number of cycles fetch has spent squashing
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 11262 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.423992 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.773203 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 8435 74.90% 74.90% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::2 191 1.70% 79.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 246 2.18% 81.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 240 2.13% 83.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 319 2.83% 86.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 123 1.09% 87.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 122 1.08% 88.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1312 11.65% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 11262 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.127963 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.645832 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 6543 # Number of cycles decode is idle
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2011-08-19 22:08:06 +02:00
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system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked
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2011-09-13 18:58:09 +02:00
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system.cpu.decode.RunCycles 2628 # Number of cycles decode is running
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2011-08-19 22:08:06 +02:00
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system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
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2011-09-13 18:58:09 +02:00
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system.cpu.decode.SquashCycles 952 # Number of cycles decode is squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction
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2011-09-13 18:58:09 +02:00
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system.cpu.decode.DecodedInsts 14071 # Number of instructions handled by decode
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2011-07-10 19:56:09 +02:00
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system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.SquashCycles 952 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 6829 # Number of cycles rename is idle
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.RunCycles 2400 # Number of cycles rename is running
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.RenamedInsts 13225 # Number of instructions processed by rename
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.RenamedOperands 12790 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 60358 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 59038 # Number of integer rename lookups
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 7101 # Number of HB maps that are undone due to squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer
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2011-09-13 18:58:09 +02:00
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system.cpu.memDep0.insertedLoads 2690 # Number of loads inserted to the mem dependence unit.
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2011-08-19 22:08:06 +02:00
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system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.iqInstsAdded 11414 # Number of instructions added to the IQ (excludes non-spec)
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.iqSquashedInstsExamined 5140 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 13918 # Number of squashed operands that are examined and possibly removed from graph
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::samples 11262 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.824188 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.485862 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 7565 67.17% 67.17% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1334 11.85% 79.02% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 849 7.54% 86.56% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 557 4.95% 91.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 476 4.23% 95.73% # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 11262 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 141 64.68% 67.43% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 5672 61.11% 61.11% # Type of FU issued
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 2322 25.02% 86.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1278 13.77% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 9282 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.473209 # Inst issue rate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.fu_busy_cnt 218 # FU busy when requested
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.fu_busy_rate 0.023486 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 30073 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 16544 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8314 # Number of integer instruction queue wakeup accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1489 # Number of loads squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 952 # Number of cycles IEW is squashing
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 11442 # Number of instructions dispatched to IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 2690 # Number of dispatched load instructions
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewExecutedInsts 8848 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2122 # Number of load instructions executed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 3 # number of nop insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_refs 3344 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 1461 # Number of branches executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_stores 1222 # Number of stores executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_rate 0.451083 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 8506 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 8330 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 3963 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 7807 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 0.424675 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.507621 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 5548 # The number of squashed insts skipped by commit
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::samples 10311 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.556590 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.365529 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 7969 77.29% 77.29% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 1090 10.57% 87.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 425 4.12% 91.98% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 280 2.72% 94.69% # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 38 0.37% 99.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 10311 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.count 5739 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 2139 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 1201 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 945 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 21353 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 23544 # The number of ROB writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.committedInsts 5739 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.int_regfile_reads 40279 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 8179 # number of integer regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fp_regfile_reads 29 # number of floating regfile reads
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 15700 # number of misc regfile reads
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 2 # number of replacements
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.total_refs 1667 # Total number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.avg_refs 5.631757 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 1667 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 1667 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 1667 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 364 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 364 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 12617500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 12617500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 12617500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 2031 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 2031 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 2031 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.179222 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.179222 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.179222 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34663.461538 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34663.461538 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34663.461538 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 9940000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 9940000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 9940000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.145741 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.145741 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.145741 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33581.081081 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_refs 15.500000 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 1789 # number of ReadReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_hits 2398 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 2398 # number of overall hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 481 # number of overall misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency 5493500 # number of ReadReq miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 16199000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 16199000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 1966 # number of ReadReq accesses(hits+misses)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 2879 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 2879 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.090031 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.167072 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.167072 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 31036.723164 # average ReadReq miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 33677.754678 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 33677.754678 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 325 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 325 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.057986 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.054185 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.054185 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 191.048911 # Cycle average of tags in use
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 191.048911 # Average occupied blocks per context
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 43 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 409 # number of overall misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 12611500 # number of ReadReq miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 14062000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 14062000 # number of overall miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34363.760218 # average ReadReq miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34381.418093 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34381.418093 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 11306000 # number of ReadReq MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31232.044199 # average ReadReq mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
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---------- End Simulation Statistics ----------
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