2004-02-06 00:23:16 +01:00
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/*
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2005-01-30 22:58:39 +01:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-02-06 00:23:16 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2004-01-22 02:14:10 +01:00
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2005-06-05 07:22:21 +02:00
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/** @file
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2004-01-26 19:26:34 +01:00
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* Tsunami I/O including PIC, PIT, RTC, DMA
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2004-01-22 02:14:10 +01:00
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*/
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2004-01-26 19:26:34 +01:00
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#include <sys/time.h>
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2004-01-22 02:14:10 +01:00
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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2004-01-22 06:36:26 +01:00
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#include "dev/tsunami_io.hh"
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2004-01-22 02:14:10 +01:00
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#include "dev/tsunami.hh"
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2005-08-15 22:59:58 +02:00
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#include "dev/pitreg.h"
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2004-06-10 19:30:58 +02:00
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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2004-01-22 02:14:10 +01:00
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#include "sim/builder.hh"
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2004-01-28 03:36:46 +01:00
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#include "dev/tsunami_cchip.hh"
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2004-06-10 19:30:58 +02:00
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#include "dev/tsunamireg.h"
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2005-01-30 22:58:39 +01:00
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#include "dev/rtcreg.h"
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2005-06-05 02:50:10 +02:00
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#include "mem/functional/memory_control.hh"
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2004-01-22 02:14:10 +01:00
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using namespace std;
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2004-01-26 19:26:34 +01:00
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2005-08-15 22:59:58 +02:00
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TsunamiIO::RTC::RTC(Tsunami* t, Tick i)
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: SimObject("RTC"), event(t, i), addr(0)
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{
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memset(clock_data, 0, sizeof(clock_data));
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stat_regA = RTCA_32768HZ | RTCA_1024HZ;
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stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
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}
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void
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TsunamiIO::RTC::set_time(time_t t)
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{
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struct tm tm;
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gmtime_r(&t, &tm);
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sec = tm.tm_sec;
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min = tm.tm_min;
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hour = tm.tm_hour;
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wday = tm.tm_wday + 1;
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mday = tm.tm_mday;
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mon = tm.tm_mon + 1;
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year = tm.tm_year;
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DPRINTFN("Real-time clock set to %s", asctime(&tm));
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}
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void
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TsunamiIO::RTC::writeAddr(const uint8_t *data)
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{
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if (*data <= RTC_STAT_REGD)
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addr = *data;
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else
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panic("RTC addresses over 0xD are not implemented.\n");
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}
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void
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TsunamiIO::RTC::writeData(const uint8_t *data)
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{
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if (addr < RTC_STAT_REGA)
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clock_data[addr] = *data;
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else {
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switch (addr) {
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case RTC_STAT_REGA:
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if (*data != (RTCA_32768HZ | RTCA_1024HZ))
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panic("Unimplemented RTC register A value write!\n");
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stat_regA = *data;
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break;
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case RTC_STAT_REGB:
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if ((*data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
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panic("Write to RTC reg B bits that are not implemented!\n");
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if (*data & RTCB_PRDC_IE) {
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if (!event.scheduled())
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event.scheduleIntr();
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} else {
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if (event.scheduled())
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event.deschedule();
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}
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stat_regB = *data;
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break;
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case RTC_STAT_REGC:
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case RTC_STAT_REGD:
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panic("RTC status registers C and D are not implemented.\n");
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break;
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}
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}
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}
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void
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TsunamiIO::RTC::readData(uint8_t *data)
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{
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if (addr < RTC_STAT_REGA)
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*data = clock_data[addr];
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else {
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switch (addr) {
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case RTC_STAT_REGA:
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// toggle UIP bit for linux
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stat_regA ^= RTCA_UIP;
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*data = stat_regA;
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break;
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case RTC_STAT_REGB:
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*data = stat_regB;
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break;
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case RTC_STAT_REGC:
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case RTC_STAT_REGD:
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*data = 0x00;
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break;
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}
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}
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}
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void
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TsunamiIO::RTC::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(addr);
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SERIALIZE_ARRAY(clock_data, sizeof(clock_data));
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SERIALIZE_SCALAR(stat_regA);
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SERIALIZE_SCALAR(stat_regB);
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// serialize the RTC event
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nameOut(os, csprintf("%s.event", name()));
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event.serialize(os);
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}
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void
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TsunamiIO::RTC::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(addr);
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UNSERIALIZE_ARRAY(clock_data, sizeof(clock_data));
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UNSERIALIZE_SCALAR(stat_regA);
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UNSERIALIZE_SCALAR(stat_regB);
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// unserialze the event
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event.unserialize(cp, csprintf("%s.event", section));
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}
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2004-01-26 19:26:34 +01:00
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2005-08-15 22:59:58 +02:00
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TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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: Event(&mainEventQueue), tsunami(t), interval(i)
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2004-01-23 19:01:32 +01:00
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{
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2004-01-26 19:26:34 +01:00
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DPRINTF(MC146818, "RTC Event Initilizing\n");
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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schedule(curTick + interval);
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2004-01-23 19:01:32 +01:00
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}
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void
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2005-08-15 22:59:58 +02:00
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|
|
TsunamiIO::RTC::RTCEvent::scheduleIntr()
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{
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schedule(curTick + interval);
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}
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void
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TsunamiIO::RTC::RTCEvent::process()
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2004-01-23 19:01:32 +01:00
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{
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2004-01-29 00:12:52 +01:00
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DPRINTF(MC146818, "RTC Timer Interrupt\n");
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
schedule(curTick + interval);
|
2004-01-26 19:26:34 +01:00
|
|
|
//Actually interrupt the processor here
|
2004-02-20 22:51:19 +01:00
|
|
|
tsunami->cchip->postRTC();
|
2004-01-23 19:01:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
const char *
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::RTC::RTCEvent::description()
|
2004-01-23 19:01:32 +01:00
|
|
|
{
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
return "tsunami RTC interrupt";
|
2004-01-23 19:01:32 +01:00
|
|
|
}
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-06-17 00:20:10 +02:00
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::RTC::RTCEvent::serialize(std::ostream &os)
|
2004-06-17 00:20:10 +02:00
|
|
|
{
|
|
|
|
Tick time = when();
|
|
|
|
SERIALIZE_SCALAR(time);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::RTC::RTCEvent::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-06-17 00:20:10 +02:00
|
|
|
{
|
|
|
|
Tick time;
|
|
|
|
UNSERIALIZE_SCALAR(time);
|
|
|
|
reschedule(time);
|
|
|
|
}
|
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::PITimer()
|
|
|
|
: SimObject("PITimer"), counter0(counter[0]), counter1(counter[1]),
|
|
|
|
counter2(counter[2])
|
|
|
|
{
|
2004-06-17 00:20:10 +02:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::writeControl(const uint8_t *data)
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
int rw;
|
|
|
|
int sel;
|
|
|
|
|
|
|
|
sel = GET_CTRL_SEL(*data);
|
|
|
|
|
|
|
|
if (sel == PIT_READ_BACK)
|
|
|
|
panic("PITimer Read-Back Command is not implemented.\n");
|
2005-03-29 14:55:44 +02:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
rw = GET_CTRL_RW(*data);
|
|
|
|
|
|
|
|
if (rw == PIT_RW_LATCH_COMMAND)
|
|
|
|
counter[sel].latchCount();
|
|
|
|
else {
|
|
|
|
counter[sel].setRW(rw);
|
|
|
|
counter[sel].setMode(GET_CTRL_MODE(*data));
|
|
|
|
counter[sel].setBCD(GET_CTRL_BCD(*data));
|
|
|
|
}
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::serialize(std::ostream &os)
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
// serialize the counters
|
|
|
|
nameOut(os, csprintf("%s.counter0", name()));
|
|
|
|
counter0.serialize(os);
|
|
|
|
|
|
|
|
nameOut(os, csprintf("%s.counter1", name()));
|
|
|
|
counter1.serialize(os);
|
|
|
|
|
|
|
|
nameOut(os, csprintf("%s.counter2", name()));
|
|
|
|
counter2.serialize(os);
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
// unserialze the counters
|
|
|
|
counter0.unserialize(cp, csprintf("%s.counter0", section));
|
|
|
|
counter1.unserialize(cp, csprintf("%s.counter1", section));
|
|
|
|
counter2.unserialize(cp, csprintf("%s.counter2", section));
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::Counter::Counter()
|
|
|
|
: SimObject("Counter"), event(this), count(0), latched_count(0), period(0),
|
|
|
|
mode(0), output_high(false), latch_on(false), read_byte(LSB),
|
|
|
|
write_byte(LSB)
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::latchCount()
|
|
|
|
{
|
|
|
|
// behave like a real latch
|
|
|
|
if(!latch_on) {
|
|
|
|
latch_on = true;
|
|
|
|
read_byte = LSB;
|
|
|
|
latched_count = count;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::read(uint8_t *data)
|
|
|
|
{
|
|
|
|
if (latch_on) {
|
|
|
|
switch (read_byte) {
|
|
|
|
case LSB:
|
|
|
|
read_byte = MSB;
|
|
|
|
*data = (uint8_t)latched_count;
|
|
|
|
break;
|
|
|
|
case MSB:
|
|
|
|
read_byte = LSB;
|
|
|
|
latch_on = false;
|
|
|
|
*data = latched_count >> 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (read_byte) {
|
|
|
|
case LSB:
|
|
|
|
read_byte = MSB;
|
|
|
|
*data = (uint8_t)count;
|
|
|
|
break;
|
|
|
|
case MSB:
|
|
|
|
read_byte = LSB;
|
|
|
|
*data = count >> 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::write(const uint8_t *data)
|
|
|
|
{
|
|
|
|
switch (write_byte) {
|
|
|
|
case LSB:
|
|
|
|
count = (count & 0xFF00) | *data;
|
|
|
|
|
|
|
|
if (event.scheduled())
|
|
|
|
event.deschedule();
|
|
|
|
output_high = false;
|
|
|
|
write_byte = MSB;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MSB:
|
|
|
|
count = (count & 0x00FF) | (*data << 8);
|
|
|
|
period = count;
|
|
|
|
|
|
|
|
if (period > 0) {
|
|
|
|
DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * event.interval);
|
|
|
|
event.schedule(curTick + count * event.interval);
|
|
|
|
}
|
|
|
|
write_byte = LSB;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::setRW(int rw_val)
|
|
|
|
{
|
|
|
|
if (rw_val != PIT_RW_16BIT)
|
|
|
|
panic("Only LSB/MSB read/write is implemented.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::setMode(int mode_val)
|
|
|
|
{
|
|
|
|
if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
|
|
|
|
mode_val != PIT_MODE_SQWAVE)
|
|
|
|
panic("PIT mode %#x is not implemented: \n", mode_val);
|
|
|
|
|
|
|
|
mode = mode_val;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::setBCD(int bcd_val)
|
|
|
|
{
|
|
|
|
if (bcd_val != PIT_BCD_FALSE)
|
|
|
|
panic("PITimer does not implement BCD counts.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
TsunamiIO::PITimer::Counter::outputHigh()
|
|
|
|
{
|
|
|
|
return output_high;
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::Counter::serialize(std::ostream &os)
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
SERIALIZE_SCALAR(count);
|
|
|
|
SERIALIZE_SCALAR(latched_count);
|
|
|
|
SERIALIZE_SCALAR(period);
|
|
|
|
SERIALIZE_SCALAR(mode);
|
|
|
|
SERIALIZE_SCALAR(output_high);
|
|
|
|
SERIALIZE_SCALAR(latch_on);
|
|
|
|
SERIALIZE_SCALAR(read_byte);
|
|
|
|
SERIALIZE_SCALAR(write_byte);
|
|
|
|
|
|
|
|
// serialize the counter event
|
|
|
|
nameOut(os, csprintf("%s.event", name()));
|
|
|
|
event.serialize(os);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
{
|
|
|
|
UNSERIALIZE_SCALAR(count);
|
|
|
|
UNSERIALIZE_SCALAR(latched_count);
|
|
|
|
UNSERIALIZE_SCALAR(period);
|
|
|
|
UNSERIALIZE_SCALAR(mode);
|
|
|
|
UNSERIALIZE_SCALAR(output_high);
|
|
|
|
UNSERIALIZE_SCALAR(latch_on);
|
|
|
|
UNSERIALIZE_SCALAR(read_byte);
|
|
|
|
UNSERIALIZE_SCALAR(write_byte);
|
|
|
|
|
|
|
|
// unserialze the counter event
|
|
|
|
event.unserialize(cp, csprintf("%s.event", section));
|
|
|
|
}
|
|
|
|
|
|
|
|
TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
|
|
|
|
: Event(&mainEventQueue)
|
|
|
|
{
|
|
|
|
interval = (Tick)(Clock::Float::s / 1193180.0);
|
|
|
|
counter = c_ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::PITimer::Counter::CounterEvent::process()
|
|
|
|
{
|
|
|
|
DPRINTF(Tsunami, "Timer Interrupt\n");
|
|
|
|
switch (counter->mode) {
|
|
|
|
case PIT_MODE_INTTC:
|
|
|
|
counter->output_high = true;
|
|
|
|
case PIT_MODE_RATEGEN:
|
|
|
|
case PIT_MODE_SQWAVE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unimplemented PITimer mode.\n");
|
|
|
|
}
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
const char *
|
|
|
|
TsunamiIO::PITimer::Counter::CounterEvent::description()
|
2004-01-23 01:02:07 +01:00
|
|
|
{
|
2005-08-15 22:59:58 +02:00
|
|
|
return "tsunami 8254 Interval timer";
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
|
|
|
|
2004-06-17 00:20:10 +02:00
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::Counter::CounterEvent::serialize(std::ostream &os)
|
2004-06-17 00:20:10 +02:00
|
|
|
{
|
2004-06-17 01:47:07 +02:00
|
|
|
Tick time = scheduled() ? when() : 0;
|
2004-06-17 00:20:10 +02:00
|
|
|
SERIALIZE_SCALAR(time);
|
|
|
|
SERIALIZE_SCALAR(interval);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-08-15 22:59:58 +02:00
|
|
|
TsunamiIO::PITimer::Counter::CounterEvent::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-06-17 00:20:10 +02:00
|
|
|
{
|
|
|
|
Tick time;
|
|
|
|
UNSERIALIZE_SCALAR(time);
|
|
|
|
UNSERIALIZE_SCALAR(interval);
|
2004-06-17 01:47:07 +02:00
|
|
|
if (time)
|
|
|
|
schedule(time);
|
2004-06-17 00:20:10 +02:00
|
|
|
}
|
|
|
|
|
2004-01-28 03:36:46 +01:00
|
|
|
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
|
2004-07-13 04:58:22 +02:00
|
|
|
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
Tick pio_latency, Tick ci)
|
|
|
|
: PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), rtc(t, ci)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-10-22 07:34:40 +02:00
|
|
|
mmu->add_child(this, RangeSize(addr, size));
|
2004-02-10 06:19:43 +01:00
|
|
|
|
2004-06-10 19:30:58 +02:00
|
|
|
if (bus) {
|
|
|
|
pioInterface = newPioInterface(name, hier, bus, this,
|
|
|
|
&TsunamiIO::cacheAccess);
|
2004-10-22 07:34:40 +02:00
|
|
|
pioInterface->addAddrRange(RangeSize(addr, size));
|
2005-06-02 03:44:00 +02:00
|
|
|
pioLatency = pio_latency * bus->clockRate;
|
2004-06-10 19:30:58 +02:00
|
|
|
}
|
|
|
|
|
2004-02-06 00:23:16 +01:00
|
|
|
// set the back pointer from tsunami to myself
|
|
|
|
tsunami->io = this;
|
|
|
|
|
2004-01-23 01:02:07 +01:00
|
|
|
timerData = 0;
|
2005-08-15 22:59:58 +02:00
|
|
|
rtc.set_time(init_time == 0 ? time(NULL) : init_time);
|
2004-01-29 01:18:29 +01:00
|
|
|
picr = 0;
|
|
|
|
picInterrupting = false;
|
2004-01-26 19:26:34 +01:00
|
|
|
}
|
|
|
|
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
Tick
|
|
|
|
TsunamiIO::frequency() const
|
|
|
|
{
|
|
|
|
return Clock::Frequency / clockInterval;
|
|
|
|
}
|
|
|
|
|
2004-01-22 02:14:10 +01:00
|
|
|
Fault
|
2004-02-03 22:59:40 +01:00
|
|
|
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-01-22 06:36:26 +01:00
|
|
|
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
|
2004-01-22 02:14:10 +01:00
|
|
|
req->vaddr, req->size, req->vaddr & 0xfff);
|
|
|
|
|
2004-11-13 20:01:38 +01:00
|
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
2004-05-14 23:34:15 +02:00
|
|
|
|
2004-01-23 01:02:07 +01:00
|
|
|
|
|
|
|
switch(req->size) {
|
2004-02-06 00:23:16 +01:00
|
|
|
case sizeof(uint8_t):
|
|
|
|
switch(daddr) {
|
2005-08-15 22:59:58 +02:00
|
|
|
// PIC1 mask read
|
|
|
|
case TSDEV_PIC1_MASK:
|
|
|
|
*(uint8_t*)data = ~mask1;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_PIC2_MASK:
|
|
|
|
*(uint8_t*)data = ~mask2;
|
|
|
|
return No_Fault;
|
2004-05-14 23:34:15 +02:00
|
|
|
case TSDEV_PIC1_ISR:
|
|
|
|
// !!! If this is modified 64bit case needs to be too
|
|
|
|
// Pal code has to do a 64 bit physical read because there is
|
|
|
|
// no load physical byte instruction
|
|
|
|
*(uint8_t*)data = picr;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_PIC2_ISR:
|
|
|
|
// PIC2 not implemnted... just return 0
|
|
|
|
*(uint8_t*)data = 0x00;
|
|
|
|
return No_Fault;
|
2005-08-15 22:59:58 +02:00
|
|
|
case TSDEV_TMR0_DATA:
|
|
|
|
pitimer.counter0.read(data);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR1_DATA:
|
|
|
|
pitimer.counter1.read(data);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR2_DATA:
|
|
|
|
pitimer.counter2.read(data);
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_RTC_DATA:
|
2005-08-15 22:59:58 +02:00
|
|
|
rtc.readData(data);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_CTRL_PORTB:
|
|
|
|
if (pitimer.counter2.outputHigh())
|
|
|
|
*data = PORTB_SPKR_HIGH;
|
|
|
|
else
|
|
|
|
*data = 0x00;
|
|
|
|
return No_Fault;
|
2004-02-06 00:23:16 +01:00
|
|
|
default:
|
|
|
|
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
|
|
|
|
}
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
case sizeof(uint32_t):
|
2004-05-14 23:34:15 +02:00
|
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
|
|
req->vaddr, req->size);
|
|
|
|
|
2004-02-06 00:23:16 +01:00
|
|
|
case sizeof(uint64_t):
|
2004-05-14 23:34:15 +02:00
|
|
|
switch(daddr) {
|
|
|
|
case TSDEV_PIC1_ISR:
|
|
|
|
// !!! If this is modified 8bit case needs to be too
|
|
|
|
// Pal code has to do a 64 bit physical read because there is
|
|
|
|
// no load physical byte instruction
|
|
|
|
*(uint64_t*)data = (uint64_t)picr;
|
|
|
|
return No_Fault;
|
|
|
|
default:
|
|
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
|
|
req->vaddr, req->size);
|
|
|
|
}
|
|
|
|
|
2004-02-06 00:23:16 +01:00
|
|
|
default:
|
|
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
|
|
req->vaddr, req->size);
|
2004-01-23 01:02:07 +01:00
|
|
|
}
|
2004-02-06 00:23:16 +01:00
|
|
|
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
|
2004-01-22 02:14:10 +01:00
|
|
|
|
|
|
|
return No_Fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
Fault
|
2004-02-03 22:59:40 +01:00
|
|
|
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-06-17 00:20:10 +02:00
|
|
|
|
|
|
|
#if TRACING_ON
|
2004-01-30 21:24:50 +01:00
|
|
|
uint8_t dt = *(uint8_t*)data;
|
|
|
|
uint64_t dt64 = dt;
|
2004-06-17 00:20:10 +02:00
|
|
|
#endif
|
2004-01-30 21:24:50 +01:00
|
|
|
|
|
|
|
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
|
|
|
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-11-13 20:01:38 +01:00
|
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
2004-01-22 06:08:48 +01:00
|
|
|
|
|
|
|
switch(req->size) {
|
2004-02-06 00:23:16 +01:00
|
|
|
case sizeof(uint8_t):
|
|
|
|
switch(daddr) {
|
|
|
|
case TSDEV_PIC1_MASK:
|
2004-05-14 23:34:15 +02:00
|
|
|
mask1 = ~(*(uint8_t*)data);
|
2004-02-06 00:23:16 +01:00
|
|
|
if ((picr & mask1) && !picInterrupting) {
|
|
|
|
picInterrupting = true;
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->postDRIR(55);
|
2004-02-06 00:23:16 +01:00
|
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
|
|
}
|
2004-05-14 23:34:15 +02:00
|
|
|
if ((!(picr & mask1)) && picInterrupting) {
|
|
|
|
picInterrupting = false;
|
|
|
|
tsunami->cchip->clearDRIR(55);
|
|
|
|
DPRINTF(Tsunami, "clearing pic interrupt\n");
|
|
|
|
}
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_PIC2_MASK:
|
|
|
|
mask2 = *(uint8_t*)data;
|
|
|
|
//PIC2 Not implemented to interrupt
|
|
|
|
return No_Fault;
|
2004-05-14 23:34:15 +02:00
|
|
|
case TSDEV_PIC1_ACK:
|
|
|
|
// clear the interrupt on the PIC
|
|
|
|
picr &= ~(1 << (*(uint8_t*)data & 0xF));
|
|
|
|
if (!(picr & mask1))
|
|
|
|
tsunami->cchip->clearDRIR(55);
|
|
|
|
return No_Fault;
|
2005-08-15 22:59:58 +02:00
|
|
|
case TSDEV_DMA1_CMND:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_CMND:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA1_MMASK:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_MMASK:
|
|
|
|
return No_Fault;
|
2004-05-14 23:34:15 +02:00
|
|
|
case TSDEV_PIC2_ACK:
|
|
|
|
return No_Fault;
|
2004-02-06 00:23:16 +01:00
|
|
|
case TSDEV_DMA1_RESET:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_RESET:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA1_MODE:
|
|
|
|
mode1 = *(uint8_t*)data;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_MODE:
|
|
|
|
mode2 = *(uint8_t*)data;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA1_MASK:
|
|
|
|
case TSDEV_DMA2_MASK:
|
|
|
|
return No_Fault;
|
2005-08-15 22:59:58 +02:00
|
|
|
case TSDEV_TMR0_DATA:
|
|
|
|
pitimer.counter0.write(data);
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
2005-08-15 22:59:58 +02:00
|
|
|
case TSDEV_TMR1_DATA:
|
|
|
|
pitimer.counter1.write(data);
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR2_DATA:
|
2005-08-15 22:59:58 +02:00
|
|
|
pitimer.counter2.write(data);
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
2005-08-15 22:59:58 +02:00
|
|
|
case TSDEV_TMR_CTRL:
|
|
|
|
pitimer.writeControl(data);
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_RTC_ADDR:
|
2005-08-15 22:59:58 +02:00
|
|
|
rtc.writeAddr(data);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_KBD:
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_RTC_DATA:
|
2005-08-15 22:59:58 +02:00
|
|
|
rtc.writeData(data);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_CTRL_PORTB:
|
|
|
|
// System Control Port B not implemented
|
|
|
|
return No_Fault;
|
2004-02-06 00:23:16 +01:00
|
|
|
default:
|
2005-08-15 22:59:58 +02:00
|
|
|
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
|
2004-02-06 00:23:16 +01:00
|
|
|
}
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
case sizeof(uint64_t):
|
|
|
|
default:
|
|
|
|
panic("I/O Write - invalid size - va %#x size %d\n",
|
|
|
|
req->vaddr, req->size);
|
2004-01-22 06:08:48 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 02:14:10 +01:00
|
|
|
|
|
|
|
return No_Fault;
|
|
|
|
}
|
|
|
|
|
2004-01-29 01:18:29 +01:00
|
|
|
void
|
|
|
|
TsunamiIO::postPIC(uint8_t bitvector)
|
|
|
|
{
|
|
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
|
|
picr |= bitvector;
|
2004-05-14 23:34:15 +02:00
|
|
|
if (picr & mask1) {
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->postDRIR(55);
|
2004-01-29 01:18:29 +01:00
|
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::clearPIC(uint8_t bitvector)
|
|
|
|
{
|
|
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
|
|
picr &= ~bitvector;
|
|
|
|
if (!(picr & mask1)) {
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->clearDRIR(55);
|
2004-01-29 01:18:29 +01:00
|
|
|
DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-06-10 19:30:58 +02:00
|
|
|
Tick
|
|
|
|
TsunamiIO::cacheAccess(MemReqPtr &req)
|
|
|
|
{
|
2004-07-13 04:58:22 +02:00
|
|
|
return curTick + pioLatency;
|
2004-06-10 19:30:58 +02:00
|
|
|
}
|
|
|
|
|
2004-01-22 02:14:10 +01:00
|
|
|
void
|
2004-01-22 06:36:26 +01:00
|
|
|
TsunamiIO::serialize(std::ostream &os)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-02-11 21:32:30 +01:00
|
|
|
SERIALIZE_SCALAR(timerData);
|
2004-06-04 20:26:17 +02:00
|
|
|
SERIALIZE_SCALAR(mask1);
|
|
|
|
SERIALIZE_SCALAR(mask2);
|
|
|
|
SERIALIZE_SCALAR(mode1);
|
|
|
|
SERIALIZE_SCALAR(mode2);
|
2004-02-11 21:32:30 +01:00
|
|
|
SERIALIZE_SCALAR(picr);
|
|
|
|
SERIALIZE_SCALAR(picInterrupting);
|
|
|
|
|
2004-06-17 01:47:07 +02:00
|
|
|
// Serialize the timers
|
2005-08-15 22:59:58 +02:00
|
|
|
nameOut(os, csprintf("%s.pitimer", name()));
|
|
|
|
pitimer.serialize(os);
|
2004-06-17 01:47:07 +02:00
|
|
|
nameOut(os, csprintf("%s.rtc", name()));
|
|
|
|
rtc.serialize(os);
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2004-01-22 06:36:26 +01:00
|
|
|
TsunamiIO::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-02-11 21:32:30 +01:00
|
|
|
UNSERIALIZE_SCALAR(timerData);
|
2004-06-04 20:26:17 +02:00
|
|
|
UNSERIALIZE_SCALAR(mask1);
|
|
|
|
UNSERIALIZE_SCALAR(mask2);
|
|
|
|
UNSERIALIZE_SCALAR(mode1);
|
|
|
|
UNSERIALIZE_SCALAR(mode2);
|
2004-02-11 21:32:30 +01:00
|
|
|
UNSERIALIZE_SCALAR(picr);
|
|
|
|
UNSERIALIZE_SCALAR(picInterrupting);
|
2004-06-17 01:47:07 +02:00
|
|
|
|
|
|
|
// Unserialize the timers
|
2005-08-15 22:59:58 +02:00
|
|
|
pitimer.unserialize(cp, csprintf("%s.pitimer", section));
|
2004-06-17 01:47:07 +02:00
|
|
|
rtc.unserialize(cp, csprintf("%s.rtc", section));
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-28 03:36:46 +01:00
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
2004-01-26 19:26:34 +01:00
|
|
|
Param<time_t> time;
|
2004-01-22 02:14:10 +01:00
|
|
|
SimObjectParam<MemoryController *> mmu;
|
|
|
|
Param<Addr> addr;
|
2004-06-10 19:30:58 +02:00
|
|
|
SimObjectParam<Bus*> io_bus;
|
2004-07-13 04:58:22 +02:00
|
|
|
Param<Tick> pio_latency;
|
2004-06-10 19:30:58 +02:00
|
|
|
SimObjectParam<HierParams *> hier;
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
Param<Tick> frequency;
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-28 03:36:46 +01:00
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
INIT_PARAM(time, "System time to use (0 for actual time"),
|
2004-01-22 02:14:10 +01:00
|
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
2004-06-10 19:30:58 +02:00
|
|
|
INIT_PARAM(addr, "Device Address"),
|
|
|
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
2004-07-13 04:58:22 +02:00
|
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
|
|
|
|
INIT_PARAM(frequency, "clock interrupt frequency")
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
CREATE_SIM_OBJECT(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-06-10 19:30:58 +02:00
|
|
|
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
io_bus, pio_latency, frequency);
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|