2016-05-31 17:55:47 +02:00
---------- Begin Simulation Statistics ----------
2016-12-05 22:48:34 +01:00
sim_seconds 0.124349 # Number of seconds simulated
sim_ticks 124348696500 # Number of ticks simulated
final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2016-05-31 17:55:47 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-12-05 22:48:34 +01:00
host_inst_rate 233440 # Simulator instruction rate (inst/s)
host_op_rate 280271 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 106315167 # Simulator tick rate (ticks/s)
host_mem_usage 292792 # Number of bytes of host memory used
host_seconds 1169.62 # Real time elapsed on the host
2016-08-12 15:12:59 +02:00
sim_insts 273037218 # Number of instructions simulated
sim_ops 327811600 # Number of ops (including micro ops) simulated
2016-05-31 17:55:47 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory
system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory
system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 261020 # Number of read requests accepted
2016-05-31 17:55:47 +02:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-12-05 22:48:34 +01:00
system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue
2016-05-31 17:55:47 +02:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-12-05 22:48:34 +01:00
system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM
2016-05-31 17:55:47 +02:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-12-05 22:48:34 +01:00
system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side
2016-05-31 17:55:47 +02:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 1258 # Per bank write bursts
system.physmem.perBankRdBursts::1 69987 # Per bank write bursts
2016-10-19 12:20:04 +02:00
system.physmem.perBankRdBursts::2 1297 # Per bank write bursts
system.physmem.perBankRdBursts::3 10756 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::4 42907 # Per bank write bursts
2016-10-19 12:20:04 +02:00
system.physmem.perBankRdBursts::5 121816 # Per bank write bursts
system.physmem.perBankRdBursts::6 153 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::7 252 # Per bank write bursts
system.physmem.perBankRdBursts::8 224 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::9 562 # Per bank write bursts
2016-10-19 12:20:04 +02:00
system.physmem.perBankRdBursts::10 7773 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::11 812 # Per bank write bursts
system.physmem.perBankRdBursts::12 1213 # Per bank write bursts
system.physmem.perBankRdBursts::13 743 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::14 657 # Per bank write bursts
system.physmem.perBankRdBursts::15 610 # Per bank write bursts
2016-05-31 17:55:47 +02:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-12-05 22:48:34 +01:00
system.physmem.totGap 124348687000 # Total gap between requests
2016-05-31 17:55:47 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.readPktSize::6 261020 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see
2016-05-31 17:55:47 +02:00
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation
system.physmem.totQLat 4577430956 # Total ticks spent queuing
system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers
system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-12-05 22:48:34 +01:00
system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s
2016-05-31 17:55:47 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-12-05 22:48:34 +01:00
system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s
2016-05-31 17:55:47 +02:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-10-19 12:20:04 +02:00
system.physmem.busUtil 1.05 # Data bus utilization in percentage
system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads
2016-05-31 17:55:47 +02:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-08-12 15:12:59 +02:00
system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing
2016-05-31 17:55:47 +02:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-12-05 22:48:34 +01:00
system.physmem.readRowHits 193077 # Number of row buffer hits during reads
2016-05-31 17:55:47 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-10-19 12:20:04 +02:00
system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads
2016-05-31 17:55:47 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-12-05 22:48:34 +01:00
system.physmem.avgGap 476395.25 # Average gap between requests
2016-10-19 12:20:04 +02:00
system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined
2016-12-05 22:48:34 +01:00
system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ)
2016-05-31 17:55:47 +02:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-12-05 22:48:34 +01:00
system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ)
system.physmem_0.averagePower 543.069721 # Core power per rank (mW)
system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states
system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states
system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states
system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ)
2016-05-31 17:55:47 +02:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-12-05 22:48:34 +01:00
system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ)
system.physmem_1.averagePower 322.109899 # Core power per rank (mW)
system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states
system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states
system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 35976625 # Number of BP lookups
system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits
2016-05-31 17:55:47 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target.
2016-10-19 12:20:04 +02:00
system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions.
2016-12-05 22:48:34 +01:00
system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches.
2016-05-31 17:55:47 +02:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 248697394 # number of cpu cycles simulated
2016-05-31 17:55:47 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed
system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2016-10-19 12:20:04 +02:00
system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps
2016-12-05 22:48:34 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch
2016-10-19 12:20:04 +02:00
system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction
2016-12-05 22:48:34 +01:00
system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups
2016-08-12 15:12:59 +02:00
system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed
2016-12-05 22:48:34 +01:00
system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available
2016-05-31 17:55:47 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued
2016-05-31 17:55:47 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued
system.cpu.iq.rate 1.364596 # Inst issue rate
system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores
2016-05-31 17:55:47 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed
2016-05-31 17:55:47 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked
2016-05-31 17:55:47 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ
2016-05-31 17:55:47 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-12-05 22:48:34 +01:00
system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute
2016-05-31 17:55:47 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu.iew.exec_nop 1402 # number of nop insts executed
system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed
system.cpu.iew.exec_branches 31542264 # Number of branches executed
system.cpu.iew.exec_stores 83131740 # Number of stores executed
system.cpu.iew.exec_rate 1.356592 # Inst execution rate
system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back
system.cpu.iew.wb_producers 153087171 # num instructions producing a value
system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value
system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit
2016-05-31 17:55:47 +02:00
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
2016-10-19 12:20:04 +02:00
system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted
2016-12-05 22:48:34 +01:00
system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu.commit.committedInsts 273037830 # Number of instructions committed
system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed
2016-05-31 17:55:47 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 168107892 # Number of memory references committed
system.cpu.commit.loads 85732275 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
2016-08-12 15:12:59 +02:00
system.cpu.commit.branches 30563525 # Number of branches committed
2016-05-31 17:55:47 +02:00
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
2016-08-12 15:12:59 +02:00
system.cpu.commit.int_insts 258331703 # Number of committed integer instructions.
2016-05-31 17:55:47 +02:00
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction
2016-05-31 17:55:47 +02:00
system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction
2016-05-31 17:55:47 +02:00
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction
2016-05-31 17:55:47 +02:00
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction
2016-05-31 17:55:47 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 573863058 # The number of ROB reads
system.cpu.rob.rob_writes 686133284 # The number of ROB writes
system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-08-12 15:12:59 +02:00
system.cpu.committedInsts 273037218 # Number of Instructions Simulated
system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated
2016-12-05 22:48:34 +01:00
system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads
system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 325196483 # number of integer regfile reads
system.cpu.int_regfile_writes 134110146 # number of integer regfile writes
system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads
system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes
system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads
system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes
system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads
2016-05-31 17:55:47 +02:00
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1542800 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
2016-10-19 12:20:04 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits
system.cpu.dcache.overall_hits::total 161951039 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses
system.cpu.dcache.overall_misses::total 3871840 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
2016-12-05 22:48:34 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked
2016-05-31 17:55:47 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked
2016-05-31 17:55:47 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks
system.cpu.dcache.writebacks::total 1542800 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1543319 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1543319 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1543330 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1543330 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27069234000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27069234000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844364193 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844364193 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1270000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1270000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses
2016-10-19 12:20:04 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20466.744191 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20466.744191 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 725912 # number of replacements
system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999634 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-19 12:20:04 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses
system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits
system.cpu.icache.overall_hits::total 81490807 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses
system.cpu.icache.overall_misses::total 733549 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked
2016-05-31 17:55:47 +02:00
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.writebacks::writebacks 725912 # number of writebacks
system.cpu.icache.writebacks::total 725912 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.prefetcher.pfSpanPage 28036 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.tagsinuse 5234.159238 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1826320 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 6292 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 290.260648 # Average number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 5154.317005 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 747 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 544 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010498 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373535 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 70559178 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 70559178 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 968252 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 968252 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1046027 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1046027 # number of WritebackClean hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 219941 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 219941 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696850 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 696850 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094381 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1094381 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 696850 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1314322 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2011172 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 696850 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1314322 # number of overall hits
system.cpu.l2cache.overall_hits::total 2011172 # number of overall hits
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 789 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 789 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29509 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 29509 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228201 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 228201 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 29509 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 258499 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 29509 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses
system.cpu.l2cache.overall_misses::total 258499 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69993500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 69993500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2629297500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2629297500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17936282000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17936282000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2629297500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 18006275500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20635573000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2629297500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 18006275500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20635573000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 968252 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 968252 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1046027 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1046027 # number of WritebackClean accesses(hits+misses)
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses)
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726359 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 726359 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322582 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1322582 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 726359 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1543312 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2269671 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 726359 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1543312 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2269671 # number of overall (read+write) accesses
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003575 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003575 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040626 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040626 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172542 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172542 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.113893 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.113893 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2529.411765 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2529.411765 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88711.660330 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88711.660330 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89101.545291 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89101.545291 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78598.612627 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78598.612627 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79828.444211 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79828.444211 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 91 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54181 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 54181 # number of HardPFReq MSHR misses
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 733 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 733 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29498 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29498 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228166 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228166 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 29498 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 228899 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 258397 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 29498 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 228899 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54181 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 312578 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203172843 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63769500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63769500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2451726000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2451726000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16564497500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16564497500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2451726000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16628267000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19079993000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2451726000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16628267000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19283165843 # number of overall MSHR miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-10-19 12:20:04 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution
2016-10-19 12:20:04 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 55629 # Total snoops (count)
2016-10-19 12:20:04 +02:00
system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter.
2016-10-19 12:20:04 +02:00
system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 260286 # Transaction distribution
2016-10-19 12:20:04 +02:00
system.membus.trans_dist::UpgradeReq 17 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::ReadExReq 733 # Transaction distribution
system.membus.trans_dist::ReadExResp 733 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::samples 261037 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::total 261037 # Request fanout histogram
system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
---------- End Simulation Statistics ----------
