2010-03-15 04:58:45 +01:00
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/*
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* Copyright (c) 2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2009-07-07 00:49:47 +02:00
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2014-10-16 11:49:49 +02:00
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#include <memory>
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2011-04-15 19:44:32 +02:00
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#include "debug/RubyDma.hh"
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2012-07-11 07:51:54 +02:00
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#include "debug/RubyStats.hh"
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2009-08-04 19:52:52 +02:00
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#include "mem/protocol/SequencerMsg.hh"
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2016-02-15 02:28:48 +01:00
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#include "mem/protocol/SequencerRequestType.hh"
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2010-03-23 02:43:53 +01:00
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#include "mem/ruby/system/DMASequencer.hh"
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2015-09-16 18:03:03 +02:00
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#include "mem/ruby/system/RubySystem.hh"
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2009-07-07 00:49:47 +02:00
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2010-01-30 05:29:17 +01:00
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DMASequencer::DMASequencer(const Params *p)
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2016-02-15 02:28:48 +01:00
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: RubyPort(p)
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2009-07-07 00:49:47 +02:00
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{
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}
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2010-03-23 02:43:53 +01:00
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void
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DMASequencer::init()
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2009-07-07 00:49:47 +02:00
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{
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2016-02-15 02:28:48 +01:00
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RubyPort::init();
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2010-03-23 02:43:53 +01:00
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m_is_busy = false;
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m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
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2016-02-18 16:50:16 +01:00
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for (const auto &s_port : slave_ports)
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s_port->sendRangeChange();
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2014-11-06 07:55:09 +01:00
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}
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2010-03-23 02:43:53 +01:00
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RequestStatus
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2011-11-15 00:44:35 +01:00
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DMASequencer::makeRequest(PacketPtr pkt)
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2009-07-07 00:49:47 +02:00
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{
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2010-08-20 20:46:12 +02:00
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if (m_is_busy) {
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return RequestStatus_BufferFull;
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}
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2015-08-14 19:04:51 +02:00
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Addr paddr = pkt->getAddr();
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2014-12-02 12:07:34 +01:00
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uint8_t* data = pkt->getPtr<uint8_t>();
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2011-11-15 00:44:35 +01:00
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int len = pkt->getSize();
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bool write = pkt->isWrite();
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2010-03-23 02:43:53 +01:00
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assert(!m_is_busy); // only support one outstanding DMA request
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m_is_busy = true;
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active_request.start_paddr = paddr;
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active_request.write = write;
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active_request.data = data;
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active_request.len = len;
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active_request.bytes_completed = 0;
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active_request.bytes_issued = 0;
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2011-11-15 00:44:35 +01:00
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active_request.pkt = pkt;
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2010-03-23 02:43:53 +01:00
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2014-10-16 11:49:49 +02:00
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std::shared_ptr<SequencerMsg> msg =
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std::make_shared<SequencerMsg>(clockEdge());
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2015-08-14 19:04:51 +02:00
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msg->getPhysicalAddress() = paddr;
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msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
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2010-06-11 08:17:06 +02:00
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msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
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2010-03-23 02:43:53 +01:00
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int offset = paddr & m_data_block_mask;
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2010-06-11 08:17:06 +02:00
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msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
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2010-03-23 02:43:53 +01:00
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len : RubySystem::getBlockSizeBytes() - offset;
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2011-02-07 07:14:19 +01:00
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if (write && (data != NULL)) {
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if (active_request.data != NULL) {
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msg->getDataBlk().setData(data, offset, msg->getLen());
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}
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2010-03-23 02:43:53 +01:00
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}
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assert(m_mandatory_q_ptr != NULL);
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2015-09-16 18:59:56 +02:00
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m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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2010-06-11 08:17:06 +02:00
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active_request.bytes_issued += msg->getLen();
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2010-03-23 02:43:53 +01:00
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return RequestStatus_Issued;
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2009-07-07 00:49:47 +02:00
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}
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2010-03-23 02:43:53 +01:00
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void
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DMASequencer::issueNext()
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2009-07-07 00:49:47 +02:00
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{
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2014-06-01 03:00:23 +02:00
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assert(m_is_busy);
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2010-03-23 02:43:53 +01:00
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active_request.bytes_completed = active_request.bytes_issued;
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if (active_request.len == active_request.bytes_completed) {
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2011-03-19 22:17:48 +01:00
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//
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// Must unset the busy flag before calling back the dma port because
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// the callback may cause a previously nacked request to be reissued
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//
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DPRINTF(RubyDma, "DMA request completed\n");
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2010-03-23 02:43:53 +01:00
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m_is_busy = false;
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2011-03-19 22:17:48 +01:00
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ruby_hit_callback(active_request.pkt);
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2010-03-23 02:43:53 +01:00
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return;
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}
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2014-10-16 11:49:49 +02:00
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std::shared_ptr<SequencerMsg> msg =
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std::make_shared<SequencerMsg>(clockEdge());
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2015-08-14 19:04:51 +02:00
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msg->getPhysicalAddress() = active_request.start_paddr +
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active_request.bytes_completed;
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2010-03-23 02:43:53 +01:00
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2015-08-14 19:04:51 +02:00
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assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
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msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
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2010-03-23 02:43:53 +01:00
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2010-06-11 08:17:06 +02:00
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msg->getType() = (active_request.write ? SequencerRequestType_ST :
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2010-03-23 02:43:53 +01:00
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SequencerRequestType_LD);
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2010-06-11 08:17:06 +02:00
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msg->getLen() =
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2010-03-23 02:43:53 +01:00
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(active_request.len -
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active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
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active_request.len - active_request.bytes_completed :
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RubySystem::getBlockSizeBytes());
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if (active_request.write) {
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2010-06-11 08:17:06 +02:00
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msg->getDataBlk().
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2010-03-23 02:43:53 +01:00
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setData(&active_request.data[active_request.bytes_completed],
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2010-06-11 08:17:06 +02:00
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0, msg->getLen());
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2010-03-23 02:43:53 +01:00
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}
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assert(m_mandatory_q_ptr != NULL);
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2015-09-16 18:59:56 +02:00
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m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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2010-06-11 08:17:06 +02:00
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active_request.bytes_issued += msg->getLen();
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2015-07-10 23:05:23 +02:00
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DPRINTF(RubyDma,
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2011-03-19 22:17:48 +01:00
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"DMA request bytes issued %d, bytes completed %d, total len %d\n",
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active_request.bytes_issued, active_request.bytes_completed,
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active_request.len);
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2009-07-07 00:49:47 +02:00
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}
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2010-03-23 02:43:53 +01:00
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void
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DMASequencer::dataCallback(const DataBlock & dblk)
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2009-07-07 00:49:47 +02:00
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{
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2014-06-01 03:00:23 +02:00
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assert(m_is_busy);
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2010-03-23 02:43:53 +01:00
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int len = active_request.bytes_issued - active_request.bytes_completed;
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int offset = 0;
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if (active_request.bytes_completed == 0)
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offset = active_request.start_paddr & m_data_block_mask;
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2014-06-01 03:00:23 +02:00
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assert(!active_request.write);
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2011-02-07 07:14:19 +01:00
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if (active_request.data != NULL) {
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memcpy(&active_request.data[active_request.bytes_completed],
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dblk.getData(offset, len), len);
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}
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2010-03-23 02:43:53 +01:00
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issueNext();
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2009-07-07 00:49:47 +02:00
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}
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2010-03-23 02:43:53 +01:00
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void
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DMASequencer::ackCallback()
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2009-07-07 00:49:47 +02:00
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{
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2010-03-23 02:43:53 +01:00
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issueNext();
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2009-07-07 00:49:47 +02:00
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}
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2012-07-11 07:51:54 +02:00
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void
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2014-11-06 07:55:09 +01:00
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DMASequencer::recordRequestType(DMASequencerRequestType requestType)
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{
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2012-07-11 07:51:54 +02:00
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DPRINTF(RubyStats, "Recorded statistic: %s\n",
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DMASequencerRequestType_to_string(requestType));
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}
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2010-01-30 05:29:17 +01:00
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DMASequencer *
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DMASequencerParams::create()
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{
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return new DMASequencer(this);
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}
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