2013-04-22 19:20:33 +02:00
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/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grass
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* Andreas Hansson
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* Sascha Bischoff
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2014-03-23 16:11:58 +01:00
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* Neha Agarwal
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2013-04-22 19:20:33 +02:00
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*/
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#include "base/random.hh"
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2013-05-30 18:54:04 +02:00
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#include "base/trace.hh"
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2013-04-22 19:20:33 +02:00
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#include "cpu/testers/traffic_gen/generators.hh"
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#include "debug/TrafficGen.hh"
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#include "proto/packet.pb.h"
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2013-05-30 18:54:04 +02:00
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BaseGen::BaseGen(const std::string& _name, MasterID master_id, Tick _duration)
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: _name(_name), masterID(master_id), duration(_duration)
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2013-04-22 19:20:33 +02:00
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{
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}
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2013-05-30 18:54:04 +02:00
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PacketPtr
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BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd,
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Request::FlagsType flags)
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2013-04-22 19:20:33 +02:00
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{
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// Create new request
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Request *req = new Request(addr, size, flags, masterID);
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2015-03-02 10:00:31 +01:00
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// Dummy PC to have PC-based prefetchers latch on; get entropy into higher
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// bits
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req->setPC(((Addr)masterID) << 2);
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2013-04-22 19:20:33 +02:00
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// Embed it in a packet
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PacketPtr pkt = new Packet(req, cmd);
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uint8_t* pkt_data = new uint8_t[req->getSize()];
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2014-12-02 12:07:43 +01:00
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pkt->dataDynamic(pkt_data);
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2013-04-22 19:20:33 +02:00
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if (cmd.isWrite()) {
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memset(pkt_data, 0xA, req->getSize());
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}
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2013-05-30 18:54:04 +02:00
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return pkt;
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2013-04-22 19:20:33 +02:00
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}
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void
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LinearGen::enter()
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{
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// reset the address and the data counter
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nextAddr = startAddr;
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dataManipulated = 0;
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}
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2013-05-30 18:54:04 +02:00
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PacketPtr
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LinearGen::getNextPacket()
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2013-04-22 19:20:33 +02:00
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{
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// choose if we generate a read or a write here
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bool isRead = readPercent != 0 &&
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2014-09-03 13:42:54 +02:00
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(readPercent == 100 || random_mt.random(0, 100) < readPercent);
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2013-04-22 19:20:33 +02:00
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assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead) ||
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readPercent != 100);
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2013-05-30 18:54:04 +02:00
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DPRINTF(TrafficGen, "LinearGen::getNextPacket: %c to addr %x, size %d\n",
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2013-04-22 19:20:33 +02:00
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isRead ? 'r' : 'w', nextAddr, blocksize);
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2013-05-30 18:54:04 +02:00
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// Add the amount of data manipulated to the total
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dataManipulated += blocksize;
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PacketPtr pkt = getPacket(nextAddr, blocksize,
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isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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2013-04-22 19:20:33 +02:00
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// increment the address
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nextAddr += blocksize;
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// If we have reached the end of the address space, reset the
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// address to the start of the range
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2013-05-30 18:54:05 +02:00
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if (nextAddr > endAddr) {
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2013-04-22 19:20:33 +02:00
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DPRINTF(TrafficGen, "Wrapping address to the start of "
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"the range\n");
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nextAddr = startAddr;
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}
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2013-05-30 18:54:05 +02:00
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return pkt;
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}
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Tick
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2013-05-30 18:54:06 +02:00
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LinearGen::nextPacketTick(bool elastic, Tick delay) const
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2013-05-30 18:54:05 +02:00
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{
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2013-04-22 19:20:33 +02:00
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// Check to see if we have reached the data limit. If dataLimit is
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// zero we do not have a data limit and therefore we will keep
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// generating requests for the entire residency in this state.
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if (dataLimit && dataManipulated >= dataLimit) {
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DPRINTF(TrafficGen, "Data limit for LinearGen reached.\n");
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// there are no more requests, therefore return MaxTick
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return MaxTick;
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} else {
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// return the time when the next request should take place
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2014-09-03 13:42:54 +02:00
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Tick wait = random_mt.random(minPeriod, maxPeriod);
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2013-05-30 18:54:06 +02:00
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// compensate for the delay experienced to not be elastic, by
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// default the value we generate is from the time we are
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// asked, so the elasticity happens automatically
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if (!elastic) {
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if (wait < delay)
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wait = 0;
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else
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wait -= delay;
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}
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return curTick() + wait;
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2013-04-22 19:20:33 +02:00
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}
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}
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void
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RandomGen::enter()
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{
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// reset the counter to zero
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dataManipulated = 0;
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}
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2013-05-30 18:54:04 +02:00
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PacketPtr
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RandomGen::getNextPacket()
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2013-04-22 19:20:33 +02:00
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{
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// choose if we generate a read or a write here
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bool isRead = readPercent != 0 &&
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2014-09-03 13:42:54 +02:00
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(readPercent == 100 || random_mt.random(0, 100) < readPercent);
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2013-04-22 19:20:33 +02:00
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assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead) ||
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readPercent != 100);
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// address of the request
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2014-09-03 13:42:54 +02:00
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Addr addr = random_mt.random(startAddr, endAddr - 1);
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2013-04-22 19:20:33 +02:00
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// round down to start address of block
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addr -= addr % blocksize;
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2013-05-30 18:54:04 +02:00
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DPRINTF(TrafficGen, "RandomGen::getNextPacket: %c to addr %x, size %d\n",
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2013-04-22 19:20:33 +02:00
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isRead ? 'r' : 'w', addr, blocksize);
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2013-05-30 18:54:04 +02:00
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// add the amount of data manipulated to the total
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2013-04-22 19:20:33 +02:00
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dataManipulated += blocksize;
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2013-05-30 18:54:04 +02:00
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// create a new request packet
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return getPacket(addr, blocksize,
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isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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2013-04-22 19:20:33 +02:00
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}
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2014-03-23 16:11:58 +01:00
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PacketPtr
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DramGen::getNextPacket()
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{
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// if this is the first of the packets in series to be generated,
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// start counting again
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if (countNumSeqPkts == 0) {
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countNumSeqPkts = numSeqPkts;
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// choose if we generate a read or a write here
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isRead = readPercent != 0 &&
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2014-09-03 13:42:54 +02:00
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(readPercent == 100 || random_mt.random(0, 100) < readPercent);
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2014-03-23 16:11:58 +01:00
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assert((readPercent == 0 && !isRead) ||
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(readPercent == 100 && isRead) ||
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readPercent != 100);
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// pick a random bank
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unsigned int new_bank =
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random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
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2014-09-20 23:17:55 +02:00
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// pick a random rank
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unsigned int new_rank =
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random_mt.random<unsigned int>(0, nbrOfRanks - 1);
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// Generate the start address of the command series
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// routine will update addr variable with bank, rank, and col
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// bits updated for random traffic mode
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genStartAddr(new_bank, new_rank);
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2014-03-23 16:11:58 +01:00
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} else {
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// increment the column by one
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if (addrMapping == 1)
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2014-09-20 23:17:55 +02:00
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// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
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// Simply increment addr by blocksize to increment the column by one
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2014-03-23 16:11:58 +01:00
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addr += blocksize;
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2014-09-20 23:17:55 +02:00
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2014-03-23 16:11:58 +01:00
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else if (addrMapping == 0) {
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2014-09-20 23:17:55 +02:00
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// addrMapping=0: RoCoRaBaCh
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// Explicity increment the column bits
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unsigned int new_col = ((addr / blocksize / nbrOfBanksDRAM / nbrOfRanks) %
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2014-03-23 16:11:58 +01:00
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(pageSize / blocksize)) + 1;
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2014-09-20 23:17:55 +02:00
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replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
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blockBits + bankBits + rankBits, new_col);
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2014-03-23 16:11:58 +01:00
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}
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}
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DPRINTF(TrafficGen, "DramGen::getNextPacket: %c to addr %x, "
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"size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
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isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
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// create a new request packet
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PacketPtr pkt = getPacket(addr, blocksize,
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isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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// add the amount of data manipulated to the total
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dataManipulated += blocksize;
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// subtract the number of packets remained to be generated
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--countNumSeqPkts;
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// return the generated packet
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return pkt;
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}
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2014-09-20 23:17:55 +02:00
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PacketPtr
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DramRotGen::getNextPacket()
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{
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// if this is the first of the packets in series to be generated,
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// start counting again
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if (countNumSeqPkts == 0) {
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countNumSeqPkts = numSeqPkts;
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// choose if we generate a read or a write here
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if (readPercent == 50) {
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if ((nextSeqCount % nbrOfBanksUtil) == 0) {
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// Change type after all banks have been rotated
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// Otherwise, keep current value
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isRead = !isRead;
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}
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} else {
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// Set randomly based on percentage
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isRead = readPercent != 0;
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}
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assert((readPercent == 0 && !isRead) ||
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(readPercent == 100 && isRead) ||
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readPercent != 100);
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// Overwrite random bank value
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// Rotate across banks
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unsigned int new_bank = nextSeqCount % nbrOfBanksUtil;
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// Overwrite random rank value
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// Will rotate to the next rank after rotating through all banks,
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// for each specified command type.
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// Use modular function to ensure that calculated rank is within
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// system limits after state transition
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unsigned int new_rank = (nextSeqCount / maxSeqCountPerRank) %
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nbrOfRanks;
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// Increment nextSeqCount
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// Roll back to 0 after completing a full rotation across
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// banks, command type, and ranks
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nextSeqCount = (nextSeqCount + 1) %
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(nbrOfRanks * maxSeqCountPerRank);
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DPRINTF(TrafficGen, "DramRotGen::getNextPacket nextSeqCount: %d "
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"new_rank: %d new_bank: %d\n",
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nextSeqCount, new_rank, new_bank);
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// Generate the start address of the command series
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// routine will update addr variable with bank, rank, and col
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// bits updated for rotation scheme
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genStartAddr(new_bank, new_rank);
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} else {
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// increment the column by one
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if (addrMapping == 1)
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// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
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// Simply increment addr by blocksize to increment the column by one
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addr += blocksize;
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else if (addrMapping == 0) {
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// addrMapping=0: RoCoRaBaCh
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// Explicity increment the column bits
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unsigned int new_col = ((addr / blocksize / nbrOfBanksDRAM / nbrOfRanks) %
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(pageSize / blocksize)) + 1;
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replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
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blockBits + bankBits + rankBits, new_col);
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}
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}
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DPRINTF(TrafficGen, "DramRotGen::getNextPacket: %c to addr %x, "
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"size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
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isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
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// create a new request packet
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PacketPtr pkt = getPacket(addr, blocksize,
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isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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// add the amount of data manipulated to the total
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dataManipulated += blocksize;
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// subtract the number of packets remained to be generated
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--countNumSeqPkts;
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// return the generated packet
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return pkt;
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}
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void
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DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
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{
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// start by picking a random address in the range
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addr = random_mt.random<Addr>(startAddr, endAddr - 1);
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|
|
|
|
|
|
|
// round down to start address of a block, i.e. a DRAM burst
|
|
|
|
addr -= addr % blocksize;
|
|
|
|
|
|
|
|
// insert the bank bits at the right spot, and align the
|
|
|
|
// address to achieve the required hit length, this involves
|
|
|
|
// finding the appropriate start address such that all
|
|
|
|
// sequential packets target successive columns in the same
|
|
|
|
// page
|
|
|
|
|
|
|
|
// for example, if we have a stride size of 192B, which means
|
|
|
|
// for LPDDR3 where burstsize = 32B we have numSeqPkts = 6,
|
|
|
|
// the address generated previously can be such that these
|
|
|
|
// 192B cross the page boundary, hence it needs to be aligned
|
|
|
|
// so that they all belong to the same page for page hit
|
|
|
|
unsigned int columns_per_page = pageSize / blocksize;
|
|
|
|
|
|
|
|
// pick a random column, but ensure that there is room for
|
|
|
|
// numSeqPkts sequential columns in the same page
|
|
|
|
unsigned int new_col =
|
|
|
|
random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
|
|
|
|
|
|
|
|
if (addrMapping == 1) {
|
|
|
|
// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
|
|
|
|
// Block bits, then page bits, then bank bits, then rank bits
|
|
|
|
replaceBits(addr, blockBits + pageBits + bankBits - 1,
|
|
|
|
blockBits + pageBits, new_bank);
|
|
|
|
replaceBits(addr, blockBits + pageBits - 1, blockBits, new_col);
|
|
|
|
if (rankBits != 0) {
|
|
|
|
replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
|
|
|
|
blockBits + pageBits + bankBits, new_rank);
|
|
|
|
}
|
|
|
|
} else if (addrMapping == 0) {
|
|
|
|
// addrMapping=0: RoCoRaBaCh
|
|
|
|
// Block bits, then bank bits, then rank bits, then page bits
|
|
|
|
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
|
|
|
|
replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
|
|
|
|
blockBits + bankBits + rankBits, new_col);
|
|
|
|
if (rankBits != 0) {
|
|
|
|
replaceBits(addr, blockBits + bankBits + rankBits - 1,
|
|
|
|
blockBits + bankBits, new_rank);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-22 19:20:33 +02:00
|
|
|
Tick
|
2013-05-30 18:54:06 +02:00
|
|
|
RandomGen::nextPacketTick(bool elastic, Tick delay) const
|
2013-04-22 19:20:33 +02:00
|
|
|
{
|
|
|
|
// Check to see if we have reached the data limit. If dataLimit is
|
|
|
|
// zero we do not have a data limit and therefore we will keep
|
|
|
|
// generating requests for the entire residency in this state.
|
|
|
|
if (dataLimit && dataManipulated >= dataLimit)
|
|
|
|
{
|
|
|
|
DPRINTF(TrafficGen, "Data limit for RandomGen reached.\n");
|
|
|
|
// No more requests. Return MaxTick.
|
|
|
|
return MaxTick;
|
|
|
|
} else {
|
2013-05-30 18:54:06 +02:00
|
|
|
// return the time when the next request should take place
|
2014-09-03 13:42:54 +02:00
|
|
|
Tick wait = random_mt.random(minPeriod, maxPeriod);
|
2013-05-30 18:54:06 +02:00
|
|
|
|
|
|
|
// compensate for the delay experienced to not be elastic, by
|
|
|
|
// default the value we generate is from the time we are
|
|
|
|
// asked, so the elasticity happens automatically
|
|
|
|
if (!elastic) {
|
|
|
|
if (wait < delay)
|
|
|
|
wait = 0;
|
|
|
|
else
|
|
|
|
wait -= delay;
|
|
|
|
}
|
|
|
|
|
|
|
|
return curTick() + wait;
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
TraceGen::InputStream::InputStream(const std::string& filename)
|
|
|
|
: trace(filename)
|
2013-08-19 09:52:32 +02:00
|
|
|
{
|
|
|
|
init();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TraceGen::InputStream::init()
|
2013-04-22 19:20:33 +02:00
|
|
|
{
|
|
|
|
// Create a protobuf message for the header and read it from the stream
|
2014-09-01 23:55:46 +02:00
|
|
|
ProtoMessage::PacketHeader header_msg;
|
2013-04-22 19:20:33 +02:00
|
|
|
if (!trace.read(header_msg)) {
|
2013-08-19 09:52:32 +02:00
|
|
|
panic("Failed to read packet header from trace\n");
|
2016-02-24 10:16:55 +01:00
|
|
|
} else if (header_msg.tick_freq() != SimClock::Frequency) {
|
|
|
|
panic("Trace was recorded with a different tick frequency %d\n",
|
|
|
|
header_msg.tick_freq());
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TraceGen::InputStream::reset()
|
|
|
|
{
|
|
|
|
trace.reset();
|
2013-08-19 09:52:32 +02:00
|
|
|
init();
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
TraceGen::InputStream::read(TraceElement& element)
|
|
|
|
{
|
2014-09-01 23:55:46 +02:00
|
|
|
ProtoMessage::Packet pkt_msg;
|
2013-04-22 19:20:33 +02:00
|
|
|
if (trace.read(pkt_msg)) {
|
|
|
|
element.cmd = pkt_msg.cmd();
|
|
|
|
element.addr = pkt_msg.addr();
|
|
|
|
element.blocksize = pkt_msg.size();
|
|
|
|
element.tick = pkt_msg.tick();
|
2013-04-23 11:07:10 +02:00
|
|
|
element.flags = pkt_msg.has_flags() ? pkt_msg.flags() : 0;
|
2013-04-22 19:20:33 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// We have reached the end of the file
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
Tick
|
2013-05-30 18:54:06 +02:00
|
|
|
TraceGen::nextPacketTick(bool elastic, Tick delay) const
|
2013-05-30 18:54:05 +02:00
|
|
|
{
|
|
|
|
if (traceComplete) {
|
|
|
|
DPRINTF(TrafficGen, "No next tick as trace is finished\n");
|
2013-04-22 19:20:33 +02:00
|
|
|
// We are at the end of the file, thus we have no more data in
|
|
|
|
// the trace Return MaxTick to signal that there will be no
|
|
|
|
// more transactions in this active period for the state.
|
|
|
|
return MaxTick;
|
|
|
|
}
|
|
|
|
|
2013-05-30 18:54:05 +02:00
|
|
|
assert(nextElement.isValid());
|
|
|
|
|
|
|
|
DPRINTF(TrafficGen, "Next packet tick is %d\n", tickOffset +
|
2013-04-22 19:20:33 +02:00
|
|
|
nextElement.tick);
|
|
|
|
|
2013-05-30 18:54:06 +02:00
|
|
|
// if the playback is supposed to be elastic, add the delay
|
|
|
|
if (elastic)
|
|
|
|
tickOffset += delay;
|
|
|
|
|
|
|
|
return std::max(tickOffset + nextElement.tick, curTick());
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TraceGen::enter()
|
|
|
|
{
|
|
|
|
// update the trace offset to the time where the state was entered.
|
|
|
|
tickOffset = curTick();
|
|
|
|
|
|
|
|
// clear everything
|
|
|
|
currElement.clear();
|
|
|
|
|
2013-05-30 18:54:05 +02:00
|
|
|
// read the first element in the file and set the complete flag
|
|
|
|
traceComplete = !trace.read(nextElement);
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
|
2013-05-30 18:54:04 +02:00
|
|
|
PacketPtr
|
|
|
|
TraceGen::getNextPacket()
|
2013-04-22 19:20:33 +02:00
|
|
|
{
|
2013-05-30 18:54:05 +02:00
|
|
|
// shift things one step forward
|
|
|
|
currElement = nextElement;
|
|
|
|
nextElement.clear();
|
|
|
|
|
|
|
|
// read the next element and set the complete flag
|
|
|
|
traceComplete = !trace.read(nextElement);
|
|
|
|
|
|
|
|
// it is the responsibility of the traceComplete flag to ensure we
|
|
|
|
// always have a valid element here
|
2013-04-22 19:20:33 +02:00
|
|
|
assert(currElement.isValid());
|
|
|
|
|
2013-05-30 18:54:04 +02:00
|
|
|
DPRINTF(TrafficGen, "TraceGen::getNextPacket: %c %d %d %d 0x%x\n",
|
2013-04-22 19:20:33 +02:00
|
|
|
currElement.cmd.isRead() ? 'r' : 'w',
|
|
|
|
currElement.addr,
|
|
|
|
currElement.blocksize,
|
2013-04-22 19:20:33 +02:00
|
|
|
currElement.tick,
|
|
|
|
currElement.flags);
|
2013-04-22 19:20:33 +02:00
|
|
|
|
2013-05-30 18:54:05 +02:00
|
|
|
PacketPtr pkt = getPacket(currElement.addr + addrOffset,
|
|
|
|
currElement.blocksize,
|
|
|
|
currElement.cmd, currElement.flags);
|
|
|
|
|
|
|
|
if (!traceComplete)
|
|
|
|
DPRINTF(TrafficGen, "nextElement: %c addr %d size %d tick %d (%d)\n",
|
|
|
|
nextElement.cmd.isRead() ? 'r' : 'w',
|
|
|
|
nextElement.addr,
|
|
|
|
nextElement.blocksize,
|
|
|
|
nextElement.tick + tickOffset,
|
|
|
|
nextElement.tick);
|
|
|
|
|
|
|
|
return pkt;
|
2013-04-22 19:20:33 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TraceGen::exit()
|
|
|
|
{
|
|
|
|
// Check if we reached the end of the trace file. If we did not
|
|
|
|
// then we want to generate a warning stating that not the entire
|
|
|
|
// trace was played.
|
|
|
|
if (!traceComplete) {
|
|
|
|
warn("Trace player %s was unable to replay the entire trace!\n",
|
|
|
|
name());
|
|
|
|
}
|
|
|
|
|
|
|
|
// Clear any flags and start over again from the beginning of the
|
|
|
|
// file
|
|
|
|
trace.reset();
|
|
|
|
}
|