2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2012-02-13 19:30:30 +01:00
|
|
|
sim_seconds 0.733278 # Number of seconds simulated
|
|
|
|
|
sim_ticks 733277720500 # Number of ticks simulated
|
|
|
|
|
final_tick 733277720500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-01-18 23:30:06 +01:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-02-13 19:30:30 +01:00
|
|
|
host_inst_rate 105807 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 144094 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 56043664 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 229440 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 13084.04 # Real time elapsed on the host
|
|
|
|
|
sim_insts 1384379038 # Number of instructions simulated
|
|
|
|
|
sim_ops 1885333791 # Number of ops (including micro ops) simulated
|
|
|
|
|
system.physmem.bytes_read 94834048 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read 211584 # Number of instructions bytes read from this memory
|
2012-01-25 18:19:50 +01:00
|
|
|
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
|
2012-02-13 19:30:30 +01:00
|
|
|
system.physmem.num_reads 1481782 # Number of read requests responded to by this memory
|
2012-01-25 18:19:50 +01:00
|
|
|
system.physmem.num_writes 66099 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
2012-02-13 19:30:30 +01:00
|
|
|
system.physmem.bw_read 129328964 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read 288546 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write 5769078 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total 135098042 # Total bandwidth to/from this memory (bytes/s)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.numCycles 1466555442 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.BPredUnit.lookups 521605883 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 398295805 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 35472641 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 324070281 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.BTBHits 281628461 # Number of BTB hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.BPredUnit.usedRAS 60884201 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 2837075 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 442389760 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 2602751444 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 521605883 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 342512662 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 710958340 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 222650773 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 102112433 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 2045 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 27281 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.CacheLines 413558926 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 12436668 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 1437090852 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.547593 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.158778 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.fetch.rateDist::0 726180548 50.53% 50.53% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 55293209 3.85% 54.38% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 113089207 7.87% 62.25% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 71780914 4.99% 67.24% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 85098858 5.92% 73.16% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 53585663 3.73% 76.89% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 33501630 2.33% 79.22% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 33512244 2.33% 81.56% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 265048579 18.44% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.fetch.rateDist::total 1437090852 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.355667 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 1.774738 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 490749730 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 81942012 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 671828843 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 10983114 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 181587153 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 78430944 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 14399 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 3525428920 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 31224 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 181587153 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 528591839 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 29769579 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 3592366 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 643071064 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 50478851 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 3416214159 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 111 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 4185905 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 40940283 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.FullRegisterEvents 71 # Number of times there has been no free registers
|
|
|
|
|
system.cpu.rename.RenamedOperands 3334777668 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 16188662039 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 15531956325 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 656705714 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.CommittedMaps 1993153607 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.UndoneMaps 1341624061 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 276669 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 271964 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 142813939 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 1064118913 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 569792794 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 34207890 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 39464438 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 3183095569 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 272489 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 2713070131 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 26125821 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 1297647909 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3029004541 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 61158 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 1437090852 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.887890 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.908228 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 520966392 36.25% 36.25% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 196978260 13.71% 49.96% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 217896132 15.16% 65.12% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 179000352 12.46% 77.58% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 155500191 10.82% 88.40% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 101390463 7.06% 95.45% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 48751651 3.39% 98.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 11023722 0.77% 99.61% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 5583689 0.39% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 1437090852 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 1973852 2.08% 2.08% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 23832 0.03% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 56484939 59.46% 61.56% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 36512276 38.44% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 1254030566 46.22% 46.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 11231291 0.41% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876617 0.25% 46.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5503438 0.20% 47.14% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 51 0.00% 47.14% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 23339517 0.86% 48.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 904708245 33.35% 81.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 506005116 18.65% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 2713070131 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.849961 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 94994899 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.035014 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 6850643246 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 4377903008 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2485399987 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 133708588 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 103168081 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 59868624 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2739540927 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 68524103 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 73975735 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 432730043 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 290479 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1327592 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 292795809 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 77 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 181587153 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16026457 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1578003 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3183438661 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 7039132 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1064118913 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 569792794 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 261469 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1577202 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 221 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1327592 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 36771149 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 9229244 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 46000393 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2613620752 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 848933154 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 99449379 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.exec_nop 70603 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1326104884 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 359304869 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 477171730 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.782149 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2573682929 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 2545268611 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1471406784 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2751379282 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.wb_rate 1.735542 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.534789 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 1384390054 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 1885344807 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 1298094205 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 211331 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 40996327 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1255503701 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.501664 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.213150 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 576634792 45.93% 45.93% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 315329042 25.12% 71.04% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 102673368 8.18% 79.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 78981369 6.29% 85.51% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 52937200 4.22% 89.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 24029706 1.91% 91.64% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 17032250 1.36% 93.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 9453700 0.75% 93.75% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 78432274 6.25% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1255503701 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committedInsts 1384390054 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 1885344807 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.refs 908385855 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 631388870 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.branches 291350233 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.int_insts 1653705627 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.bw_lim_events 78432274 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rob.rob_reads 4360492094 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 6548474997 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1306597 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 29464590 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1384379038 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 1885333791 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1384379038 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 1.059360 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.059360 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.943966 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.943966 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12901082944 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2417885668 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 70910494 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 51358984 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 4077651963 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 13776278 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 29135 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1664.054518 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 413522379 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 30834 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 13411.246643 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 1664.054518 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.812527 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.812527 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 413522385 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 413522385 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 413522385 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 413522385 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 413522385 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 413522385 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 36541 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 36541 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 36541 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 36541 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 36541 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 36541 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 319633500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 319633500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 319633500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 319633500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 319633500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 319633500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 413558926 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 413558926 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 413558926 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 413558926 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 413558926 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 413558926 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8747.256506 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 817 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 817 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 817 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 817 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 817 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 817 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 35724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 35724 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 35724 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 35724 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 35724 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191012000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 191012000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191012000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 191012000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191012000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 191012000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5346.881648 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.replacements 1532451 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.804050 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1033430950 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1536547 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 672.567094 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 312701000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.804050 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 757273946 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 757273946 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 276114941 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 276114941 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 12925 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 12925 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11673 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 11673 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 1033388887 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 1033388887 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 1033388887 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 1033388887 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2471866 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 2471866 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 820737 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 820737 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3292603 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3292603 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3292603 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3292603 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82130752000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 82130752000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 28580919500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 28580919500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 112500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 110711671500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 110711671500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 110711671500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 110711671500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 759745812 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 759745812 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12928 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 12928 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11673 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11673 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 1036681490 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 1036681490 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 1036681490 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 1036681490 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003254 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000232 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.003176 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.003176 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33226.215337 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34823.481213 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20875 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 106628 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 106628 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1008030 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1008030 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743137 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 743137 # number of WriteReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1751167 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 1751167 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1751167 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 1751167 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463836 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1463836 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77600 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77600 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1541436 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1541436 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1541436 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1541436 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029558000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029558000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2501048000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2501048000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52530606000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 52530606000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52530606000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 52530606000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001927 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34177.023929 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.005551 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.005551 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.replacements 1480282 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31969.351764 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 87232 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.057655 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 2974.802927 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 59.292981 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28935.255856 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.090784 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001809 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.883034 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.975627 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 27526 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 51416 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 78942 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 106628 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 106628 # number of Writeback hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6631 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 6631 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 27526 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 58047 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 85573 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 27526 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 58047 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 85573 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3310 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1412420 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 1415730 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4885 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 4885 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3310 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 1478500 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 1481810 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3310 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 1478500 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 1481810 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113464000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48455616000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 48569080000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252382000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2252382000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 113464000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 50707998000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 50821462000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 113464000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 50707998000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 50821462000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30836 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1463836 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1494672 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 106628 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 106628 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4889 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 4889 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72711 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 72711 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 30836 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1536547 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 1567383 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 30836 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1536547 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 1567383 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107342 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964876 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999182 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908803 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107342 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.962222 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107342 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.962222 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34279.154079 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.803925 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.684019 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34279.154079 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.921204 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34279.154079 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.921204 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3306 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412396 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1415702 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4885 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4885 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3306 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1478476 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 1481782 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3306 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1478476 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 1481782 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102729500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43881583500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984313000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 151435000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 151435000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048541500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048541500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102729500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45930125000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 46032854500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102729500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45930125000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 46032854500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964859 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999182 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908803 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.653962 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.895338 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.930690 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
