2006-06-28 17:02:14 +02:00
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/*
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2013-06-27 11:49:50 +02:00
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* Copyright (c) 2012-2013 ARM Limited
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2012-11-02 17:32:02 +01:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-06-28 17:02:14 +02:00
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Declaration of a LRU tag store.
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*/
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2009-05-17 23:34:52 +02:00
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#ifndef __MEM_CACHE_TAGS_LRU_HH__
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#define __MEM_CACHE_TAGS_LRU_HH__
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2006-06-28 17:02:14 +02:00
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2009-05-17 23:34:52 +02:00
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#include <cassert>
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2007-01-27 00:48:51 +01:00
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#include <cstring>
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2006-06-28 17:02:14 +02:00
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#include <list>
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2008-02-10 23:45:25 +01:00
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#include "mem/cache/tags/base.hh"
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2013-06-27 11:49:50 +02:00
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#include "mem/cache/tags/cacheset.hh"
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2011-04-15 19:44:06 +02:00
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#include "mem/cache/blk.hh"
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2009-05-17 23:34:52 +02:00
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#include "mem/packet.hh"
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2013-06-27 11:49:50 +02:00
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#include "params/LRU.hh"
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2006-06-28 17:02:14 +02:00
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class BaseCache;
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/**
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* A LRU cache tag store.
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2012-09-25 18:49:41 +02:00
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* @sa \ref gem5MemorySystem "gem5 Memory System"
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2006-06-28 17:02:14 +02:00
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*/
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class LRU : public BaseTags
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{
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public:
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/** Typedef the block type used in this tag store. */
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2010-02-23 18:33:09 +01:00
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typedef CacheBlk BlkType;
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2006-06-28 17:02:14 +02:00
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/** Typedef for a list of pointers to the local block class. */
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2010-02-23 18:33:09 +01:00
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typedef std::list<BlkType*> BlkList;
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2013-06-27 11:49:50 +02:00
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/** Typedef the set type used in this tag store. */
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typedef CacheSet<CacheBlk> SetType;
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2009-06-05 08:21:12 +02:00
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2006-06-28 17:02:14 +02:00
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protected:
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/** The associativity of the cache. */
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2009-06-05 08:21:12 +02:00
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const unsigned assoc;
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2013-06-27 11:49:50 +02:00
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/** The number of sets in the cache. */
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const unsigned numSets;
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2014-01-24 22:29:30 +01:00
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/** Whether tags and data are accessed sequentially. */
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const bool sequentialAccess;
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2006-06-28 17:02:14 +02:00
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/** The cache sets. */
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2013-06-27 11:49:50 +02:00
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SetType *sets;
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2006-06-28 17:02:14 +02:00
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/** The cache blocks. */
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2010-02-23 18:33:09 +01:00
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BlkType *blks;
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2006-06-28 17:02:14 +02:00
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/** The data blocks, 1 per cache block. */
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uint8_t *dataBlks;
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/** The amount to shift the address to get the set. */
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int setShift;
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/** The amount to shift the address to get the tag. */
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int tagShift;
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/** Mask out all bits that aren't part of the set index. */
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unsigned setMask;
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/** Mask out all bits that aren't part of the block offset. */
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unsigned blkMask;
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public:
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2013-06-27 11:49:50 +02:00
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/** Convenience typedef. */
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typedef LRUParams Params;
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2006-06-28 17:02:14 +02:00
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/**
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* Construct and initialize this tag store.
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*/
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2013-06-27 11:49:50 +02:00
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LRU(const Params *p);
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2006-06-28 17:02:14 +02:00
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/**
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* Destructor
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*/
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virtual ~LRU();
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/**
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* Return the block size.
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* @return the block size.
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*/
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2009-06-05 08:21:12 +02:00
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unsigned
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getBlockSize() const
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2006-06-28 17:02:14 +02:00
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{
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return blkSize;
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}
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/**
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* Return the subblock size. In the case of LRU it is always the block
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* size.
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* @return The block size.
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*/
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2009-06-05 08:21:12 +02:00
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unsigned
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getSubBlockSize() const
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2006-06-28 17:02:14 +02:00
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{
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return blkSize;
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}
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/**
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2006-12-19 08:07:52 +01:00
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* Invalidate the given block.
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* @param blk The block to invalidate.
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2006-06-28 17:02:14 +02:00
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*/
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2012-09-11 20:14:49 +02:00
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void invalidate(BlkType *blk);
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2006-06-28 17:02:14 +02:00
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/**
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2008-11-04 17:35:57 +01:00
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* Access block and update replacement data. May not succeed, in which case
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* NULL pointer is returned. This has all the implications of a cache
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* access and should only be used as such. Returns the access latency as a side effect.
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2006-06-28 17:02:14 +02:00
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* @param addr The address to find.
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* @param asid The address space ID.
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* @param lat The access latency.
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* @return Pointer to the cache block if found.
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*/
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2012-10-15 14:10:54 +02:00
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BlkType* accessBlock(Addr addr, Cycles &lat, int context_src);
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2006-06-28 17:02:14 +02:00
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/**
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* Finds the given address in the cache, do not update replacement data.
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2008-11-04 17:35:57 +01:00
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* i.e. This is a no-side-effect find of a block.
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2006-06-28 17:02:14 +02:00
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* @param addr The address to find.
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* @param asid The address space ID.
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* @return Pointer to the cache block if found.
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*/
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2010-02-23 18:33:09 +01:00
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BlkType* findBlock(Addr addr) const;
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2006-06-28 17:02:14 +02:00
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/**
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2008-11-04 17:35:58 +01:00
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* Find a block to evict for the address provided.
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* @param addr The addr to a find a replacement candidate for.
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2006-06-28 17:02:14 +02:00
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* @param writebacks List for any writebacks to be performed.
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2008-11-04 17:35:58 +01:00
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* @return The candidate block.
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2006-06-28 17:02:14 +02:00
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*/
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2010-02-23 18:33:09 +01:00
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BlkType* findVictim(Addr addr, PacketList &writebacks);
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2008-11-04 17:35:58 +01:00
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/**
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* Insert the new block into the cache. For LRU this means inserting into
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* the MRU position of the set.
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2013-06-27 11:49:50 +02:00
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* @param pkt Packet holding the address to update
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2008-11-04 17:35:58 +01:00
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* @param blk The block to update.
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*/
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2013-06-27 11:49:50 +02:00
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void insertBlock(PacketPtr pkt, BlkType *blk);
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2006-06-28 17:02:14 +02:00
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/**
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* Generate the tag from the given address.
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* @param addr The address to get the tag from.
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* @return The tag of the address.
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*/
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Addr extractTag(Addr addr) const
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{
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return (addr >> tagShift);
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}
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/**
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* Calculate the set index from the address.
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* @param addr The address to get the set from.
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* @return The set index of the address.
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*/
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int extractSet(Addr addr) const
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{
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return ((addr >> setShift) & setMask);
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}
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/**
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* Get the block offset from an address.
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* @param addr The address to get the offset of.
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* @return The block offset.
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*/
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int extractBlkOffset(Addr addr) const
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{
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return (addr & blkMask);
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}
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/**
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* Align an address to the block size.
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* @param addr the address to align.
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* @return The block address.
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*/
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Addr blkAlign(Addr addr) const
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{
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return (addr & ~(Addr)blkMask);
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}
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/**
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* Regenerate the block address from the tag.
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* @param tag The tag of the block.
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* @param set The set of the block.
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* @return The block address.
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*/
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Addr regenerateBlkAddr(Addr tag, unsigned set) const
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{
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return ((tag << tagShift) | ((Addr)set << setShift));
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}
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/**
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* Return the hit latency.
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* @return the hit latency.
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*/
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2012-10-15 14:10:54 +02:00
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Cycles getHitLatency() const
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2006-06-28 17:02:14 +02:00
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{
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return hitLatency;
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}
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2010-08-23 18:18:41 +02:00
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/**
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*iterated through all blocks and clear all locks
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*Needed to clear all lock tracking at once
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*/
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virtual void clearLocks();
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2006-06-28 17:02:14 +02:00
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/**
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* Called at end of simulation to complete average block reference stats.
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*/
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virtual void cleanupRefs();
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2012-11-02 17:32:02 +01:00
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2013-04-22 19:20:33 +02:00
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/**
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* Print all tags used
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*/
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virtual std::string print() const;
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2014-01-24 22:29:30 +01:00
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/**
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* Called prior to dumping stats to compute task occupancy
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*/
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virtual void computeStats();
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2012-11-02 17:32:02 +01:00
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/**
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* Visit each block in the tag store and apply a visitor to the
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* block.
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*
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* The visitor should be a function (or object that behaves like a
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* function) that takes a cache block reference as its parameter
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* and returns a bool. A visitor can request the traversal to be
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* stopped by returning false, returning true causes it to be
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* called for the next block in the tag store.
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*
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* \param visitor Visitor to call on each block.
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*/
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template <typename V>
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void forEachBlk(V &visitor) {
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for (unsigned i = 0; i < numSets * assoc; ++i) {
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if (!visitor(blks[i]))
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return;
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}
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}
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2006-06-28 17:02:14 +02:00
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};
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2009-05-17 23:34:52 +02:00
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#endif // __MEM_CACHE_TAGS_LRU_HH__
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