2014-07-28 18:23:23 +02:00
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/*
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2015-07-30 09:41:42 +02:00
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* Copyright (c) 2012-2014 ARM Limited
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2014-07-28 18:23:23 +02:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Declaration of a base set associative tag store.
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*/
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#ifndef __MEM_CACHE_TAGS_BASESETASSOC_HH__
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#define __MEM_CACHE_TAGS_BASESETASSOC_HH__
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#include <cassert>
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#include <cstring>
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#include <list>
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#include "mem/cache/base.hh"
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#include "mem/cache/blk.hh"
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2016-05-26 12:56:24 +02:00
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#include "mem/cache/tags/base.hh"
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#include "mem/cache/tags/cacheset.hh"
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2014-07-28 18:23:23 +02:00
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#include "mem/packet.hh"
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#include "params/BaseSetAssoc.hh"
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/**
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* A BaseSetAssoc cache tag store.
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* @sa \ref gem5MemorySystem "gem5 Memory System"
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*
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* The BaseSetAssoc tags provide a base, as well as the functionality
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* common to any set associative tags. Any derived class must implement
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* the methods related to the specifics of the actual replacment policy.
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* These are:
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*
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* BlkType* accessBlock();
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* BlkType* findVictim();
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* void insertBlock();
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* void invalidate();
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*/
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class BaseSetAssoc : public BaseTags
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{
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public:
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/** Typedef the block type used in this tag store. */
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typedef CacheBlk BlkType;
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/** Typedef the set type used in this tag store. */
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typedef CacheSet<CacheBlk> SetType;
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protected:
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/** The associativity of the cache. */
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const unsigned assoc;
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2015-07-30 09:41:42 +02:00
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/** The allocatable associativity of the cache (alloc mask). */
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unsigned allocAssoc;
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2014-07-28 18:23:23 +02:00
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/** The number of sets in the cache. */
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const unsigned numSets;
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/** Whether tags and data are accessed sequentially. */
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const bool sequentialAccess;
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/** The cache sets. */
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SetType *sets;
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/** The cache blocks. */
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BlkType *blks;
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/** The data blocks, 1 per cache block. */
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uint8_t *dataBlks;
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/** The amount to shift the address to get the set. */
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int setShift;
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/** The amount to shift the address to get the tag. */
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int tagShift;
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/** Mask out all bits that aren't part of the set index. */
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unsigned setMask;
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/** Mask out all bits that aren't part of the block offset. */
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unsigned blkMask;
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public:
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/** Convenience typedef. */
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typedef BaseSetAssocParams Params;
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/**
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* Construct and initialize this tag store.
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*/
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BaseSetAssoc(const Params *p);
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/**
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* Destructor
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*/
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virtual ~BaseSetAssoc();
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2015-07-30 09:41:42 +02:00
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/**
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* Find the cache block given set and way
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* @param set The set of the block.
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* @param way The way of the block.
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* @return The cache block.
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*/
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2015-10-12 10:08:01 +02:00
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CacheBlk *findBlockBySetAndWay(int set, int way) const override;
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2015-07-30 09:41:42 +02:00
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2014-07-28 18:23:23 +02:00
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/**
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* Invalidate the given block.
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* @param blk The block to invalidate.
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*/
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2015-10-12 10:08:01 +02:00
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void invalidate(CacheBlk *blk) override
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2014-07-28 18:23:23 +02:00
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{
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assert(blk);
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assert(blk->isValid());
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tagsInUse--;
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assert(blk->srcMasterId < cache->system->maxMasters());
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occupancies[blk->srcMasterId]--;
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blk->srcMasterId = Request::invldMasterId;
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blk->task_id = ContextSwitchTaskId::Unknown;
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blk->tickInserted = curTick();
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}
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/**
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* Access block and update replacement data. May not succeed, in which case
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2016-05-26 12:56:24 +02:00
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* nullptr is returned. This has all the implications of a cache
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2014-07-28 18:23:23 +02:00
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* access and should only be used as such. Returns the access latency as a
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* side effect.
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* @param addr The address to find.
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* @param is_secure True if the target memory space is secure.
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* @param lat The access latency.
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* @return Pointer to the cache block if found.
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*/
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2017-02-21 15:14:44 +01:00
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CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
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2014-07-28 18:23:23 +02:00
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{
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Addr tag = extractTag(addr);
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int set = extractSet(addr);
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BlkType *blk = sets[set].findBlk(tag, is_secure);
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// Access all tags in parallel, hence one in each way. The data side
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// either accesses all blocks in parallel, or one block sequentially on
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// a hit. Sequential access with a miss doesn't access data.
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2015-07-30 09:41:42 +02:00
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tagAccesses += allocAssoc;
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2014-07-28 18:23:23 +02:00
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if (sequentialAccess) {
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2016-05-26 12:56:24 +02:00
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if (blk != nullptr) {
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2014-07-28 18:23:23 +02:00
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dataAccesses += 1;
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}
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} else {
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2015-07-30 09:41:42 +02:00
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dataAccesses += allocAssoc;
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2014-07-28 18:23:23 +02:00
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}
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2016-05-26 12:56:24 +02:00
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if (blk != nullptr) {
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2016-11-30 23:10:27 +01:00
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// If a cache hit
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lat = accessLatency;
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// Check if the block to be accessed is available. If not,
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// apply the accessLatency on top of block->whenReady.
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if (blk->whenReady > curTick() &&
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cache->ticksToCycles(blk->whenReady - curTick()) >
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accessLatency) {
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lat = cache->ticksToCycles(blk->whenReady - curTick()) +
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accessLatency;
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2014-07-28 18:23:23 +02:00
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}
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blk->refCount += 1;
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2016-11-30 23:10:27 +01:00
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} else {
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// If a cache miss
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lat = lookupLatency;
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2014-07-28 18:23:23 +02:00
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}
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return blk;
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}
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/**
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* Finds the given address in the cache, do not update replacement data.
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* i.e. This is a no-side-effect find of a block.
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* @param addr The address to find.
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* @param is_secure True if the target memory space is secure.
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* @param asid The address space ID.
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* @return Pointer to the cache block if found.
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*/
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2015-10-12 10:08:01 +02:00
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CacheBlk* findBlock(Addr addr, bool is_secure) const override;
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2014-07-28 18:23:23 +02:00
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/**
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* Find an invalid block to evict for the address provided.
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* If there are no invalid blocks, this will return the block
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* in the least-recently-used position.
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* @param addr The addr to a find a replacement candidate for.
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* @return The candidate block.
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*/
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2015-10-12 10:08:01 +02:00
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CacheBlk* findVictim(Addr addr) override
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2014-07-28 18:23:23 +02:00
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{
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2016-05-26 12:56:24 +02:00
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BlkType *blk = nullptr;
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2014-07-28 18:23:23 +02:00
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int set = extractSet(addr);
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// prefer to evict an invalid block
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2015-07-30 09:41:42 +02:00
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for (int i = 0; i < allocAssoc; ++i) {
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2014-07-28 18:23:23 +02:00
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blk = sets[set].blks[i];
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2015-07-30 09:41:42 +02:00
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if (!blk->isValid())
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2014-07-28 18:23:23 +02:00
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break;
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}
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return blk;
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}
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/**
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* Insert the new block into the cache.
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* @param pkt Packet holding the address to update
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* @param blk The block to update.
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*/
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2015-10-12 10:08:01 +02:00
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void insertBlock(PacketPtr pkt, CacheBlk *blk) override
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2014-07-28 18:23:23 +02:00
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{
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Addr addr = pkt->getAddr();
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MasterID master_id = pkt->req->masterId();
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uint32_t task_id = pkt->req->taskId();
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2014-08-13 12:57:24 +02:00
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2014-07-28 18:23:23 +02:00
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if (!blk->isTouched) {
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tagsInUse++;
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blk->isTouched = true;
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if (!warmedUp && tagsInUse.value() >= warmupBound) {
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warmedUp = true;
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warmupCycle = curTick();
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}
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}
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// If we're replacing a block that was previously valid update
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// stats for it. This can't be done in findBlock() because a
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// found block might not actually be replaced there if the
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// coherence protocol says it can't be.
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if (blk->isValid()) {
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replacements[0]++;
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totalRefs += blk->refCount;
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++sampledRefs;
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blk->refCount = 0;
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// deal with evicted block
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assert(blk->srcMasterId < cache->system->maxMasters());
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occupancies[blk->srcMasterId]--;
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blk->invalidate();
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}
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blk->isTouched = true;
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2014-08-13 12:57:24 +02:00
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2014-07-28 18:23:23 +02:00
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// Set tag for new block. Caller is responsible for setting status.
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blk->tag = extractTag(addr);
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// deal with what we are bringing in
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assert(master_id < cache->system->maxMasters());
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occupancies[master_id]++;
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blk->srcMasterId = master_id;
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blk->task_id = task_id;
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blk->tickInserted = curTick();
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// We only need to write into one tag and one data block.
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tagAccesses += 1;
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dataAccesses += 1;
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}
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2015-07-30 09:41:42 +02:00
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/**
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* Limit the allocation for the cache ways.
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* @param ways The maximum number of ways available for replacement.
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*/
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2015-10-12 10:08:01 +02:00
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virtual void setWayAllocationMax(int ways) override
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2015-07-30 09:41:42 +02:00
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{
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fatal_if(ways < 1, "Allocation limit must be greater than zero");
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allocAssoc = ways;
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}
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/**
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* Get the way allocation mask limit.
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* @return The maximum number of ways available for replacement.
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*/
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2015-10-12 10:08:01 +02:00
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virtual int getWayAllocationMax() const override
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2015-07-30 09:41:42 +02:00
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{
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return allocAssoc;
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}
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2014-07-28 18:23:23 +02:00
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/**
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* Generate the tag from the given address.
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* @param addr The address to get the tag from.
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* @return The tag of the address.
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*/
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2015-10-12 10:08:01 +02:00
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Addr extractTag(Addr addr) const override
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2014-07-28 18:23:23 +02:00
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{
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return (addr >> tagShift);
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}
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/**
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* Calculate the set index from the address.
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* @param addr The address to get the set from.
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* @return The set index of the address.
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*/
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2015-10-12 10:08:01 +02:00
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int extractSet(Addr addr) const override
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2014-07-28 18:23:23 +02:00
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{
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return ((addr >> setShift) & setMask);
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}
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/**
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* Align an address to the block size.
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* @param addr the address to align.
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* @return The block address.
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*/
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Addr blkAlign(Addr addr) const
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{
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return (addr & ~(Addr)blkMask);
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}
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/**
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* Regenerate the block address from the tag.
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* @param tag The tag of the block.
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* @param set The set of the block.
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* @return The block address.
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*/
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2015-10-12 10:08:01 +02:00
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Addr regenerateBlkAddr(Addr tag, unsigned set) const override
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2014-07-28 18:23:23 +02:00
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{
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return ((tag << tagShift) | ((Addr)set << setShift));
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}
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/**
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* Called at end of simulation to complete average block reference stats.
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*/
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2015-10-12 10:08:01 +02:00
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void cleanupRefs() override;
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2014-07-28 18:23:23 +02:00
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/**
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* Print all tags used
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*/
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2015-10-12 10:08:01 +02:00
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std::string print() const override;
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2014-07-28 18:23:23 +02:00
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/**
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* Called prior to dumping stats to compute task occupancy
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*/
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2015-10-12 10:08:01 +02:00
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void computeStats() override;
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2014-07-28 18:23:23 +02:00
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/**
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* Visit each block in the tag store and apply a visitor to the
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* block.
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*
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* The visitor should be a function (or object that behaves like a
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* function) that takes a cache block reference as its parameter
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* and returns a bool. A visitor can request the traversal to be
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* stopped by returning false, returning true causes it to be
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* called for the next block in the tag store.
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*
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* \param visitor Visitor to call on each block.
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*/
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2015-10-12 10:07:59 +02:00
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void forEachBlk(CacheBlkVisitor &visitor) override {
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2014-07-28 18:23:23 +02:00
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for (unsigned i = 0; i < numSets * assoc; ++i) {
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if (!visitor(blks[i]))
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return;
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}
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}
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};
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#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__
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