2006-01-29 23:25:54 +01:00
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////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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2006-03-07 10:33:10 +01:00
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decode OP default Trap::unknown({{IllegalInstruction}}) {
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2006-01-29 23:25:54 +01:00
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0x0: decode OP2 {
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2006-03-07 10:33:10 +01:00
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0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
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0x1: Branch::bpcc({{
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switch((CC12 << 1) | CC02)
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{
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case 1:
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case 3:
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fault = new IllegalInstruction;
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case 0:
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if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
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;//branchHere
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break;
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case 2:
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if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
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;//branchHere
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break;
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}
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}});//BPcc
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0x2: Branch::bicc({{
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if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
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;//branchHere
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}});//Bicc
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0x3: Branch::bpr({{
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switch(RCOND)
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{
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case 0:
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case 4:
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fault = new IllegalInstruction;
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case 1:
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if(Rs1 == 0)
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;//branchHere
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break;
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case 2:
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if(Rs1 <= 0)
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;//branchHere
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break;
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case 3:
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if(Rs1 < 0)
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;//branchHere
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break;
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case 5:
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if(Rs1 != 0)
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;//branchHere
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break;
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case 6:
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if(Rs1 > 0)
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;//branchHere
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break;
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case 7:
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if(Rs1 >= 0)
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;//branchHere
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break;
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}
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2006-01-29 23:25:54 +01:00
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}}); //BPr
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2006-03-07 10:33:10 +01:00
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//SETHI (or NOP if rd == 0 and imm == 0)
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0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
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2006-01-29 23:25:54 +01:00
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0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
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0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc
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}
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0x1: Branch::call({{
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//branch here
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Rd = xc->pc;
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}});
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0x2: decode OP3 {
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2006-03-07 10:33:10 +01:00
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format IntegerOp {
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0x00: add({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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Rd = Rs1.sdw + val2;
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}});//ADD
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0x01: and({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & val2;
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}});//AND
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0x02: or({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | val2;
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}});//OR
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0x03: xor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw ^ val2;
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}});//XOR
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0x04: sub({{
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int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
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Rd = Rs1.sdw + val2;
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}});//SUB
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0x05: andn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & ~val2;
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}});//ANDN
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0x06: orn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | ~val2;
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}});//ORN
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0x07: xnor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = ~(Rs1.udw ^ val2);
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}});//XNOR
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0x08: addc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd = Rs1.sdw + val2 + carryin;
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}});//ADDC
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0x09: mulx({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 * val2;
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}});//MULX
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0x0A: umul({{
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uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
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}});//UMUL
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0x0B: smul({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
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rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
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}});//SMUL
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0x0C: subc({{
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int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
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int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd.sdw = Rs1.sdw + val2 + carryin;
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}});//SUBC
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0x0D: udivx({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) throw division_by_zero;
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Rd.udw = Rs1.udw / val2;
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}});//UDIVX
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0x0E: udiv({{
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uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32)
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| Rs1.udw<31:0>) / val2;
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int32_t overflow = (resTemp<63:32> != 0);
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if(overflow)
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rd.udw = resTemp = 0xFFFFFFFF;
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else
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rd.udw = resTemp;
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}}); //UDIV
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0x0F: sdiv({{
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int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) |
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Rs1.sdw<31:0>) / val2;
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resTemp = Rd.sdw;
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int32_t overflow = (resTemp<63:31> != 0);
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int32_t underflow =
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(resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow)
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rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow)
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rd.udw = resTemp = 0xFFFFFFFF80000000;
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else
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rd.udw = resTemp;
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}});//SDIV
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}
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format IntegerOpCc {
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0x10: addcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDcc
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0x11: andcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & val2;}},
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{{0}},{{0}},{{0}},{{0}});//ANDcc
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0x12: orcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | val2;}},
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{{0}},{{0}},{{0}},{{0}});//ORcc
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0x13: xorcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 ^ val2;}},
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{{0}},{{0}},{{0}},{{0}});//XORcc
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0x14: subcc({{
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 - val2;}},
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{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~val2) >> 1) +
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((Rs1 | ~val2) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBcc
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0x15: andncc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & ~val2;}},
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{{0}},{{0}},{{0}},{{0}});//ANDNcc
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0x16: orncc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | ~val2;}},
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{{0}},{{0}},{{0}},{{0}});//ORNcc
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0x17: xnorcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = ~(Rs1 ^ val2);}},
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{{0}},{{0}},{{0}},{{0}});//XNORcc
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0x18: addccc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
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+ carryin)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) +
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((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDCcc
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0x1A: umulcc({{
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uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});//UMULcc
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2006-01-29 23:25:54 +01:00
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0x1B: smulcc({{
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2006-03-07 10:33:10 +01:00
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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2006-01-29 23:25:54 +01:00
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Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
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,{{0}},{{0}},{{0}},{{0}});//SMULcc
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0x1C: subccc({{
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2006-03-07 10:33:10 +01:00
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
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int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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2006-01-29 23:25:54 +01:00
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Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
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{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBCcc
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0x1D: udivxcc({{
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2006-03-07 10:33:10 +01:00
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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2006-01-29 23:25:54 +01:00
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if(val2 == 0) throw division_by_zero;
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Rd.udw = Rs1.udw / val2;}}
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,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
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0x1E: udivcc({{
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2006-03-07 10:33:10 +01:00
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uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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2006-01-29 23:25:54 +01:00
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if(val2 == 0) throw division_by_zero;
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2006-03-07 10:33:10 +01:00
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resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
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int32_t overflow = (resTemp<63:32> != 0);
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2006-01-29 23:25:54 +01:00
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if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
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else rd.udw = resTemp;}},
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{{0}},
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{{overflow}},
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{{0}},
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{{0}}
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);//UDIVcc
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0x1F: sdivcc({{
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2006-03-07 10:33:10 +01:00
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int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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2006-01-29 23:25:54 +01:00
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if(val2 == 0) throw division_by_zero;
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2006-03-07 10:33:10 +01:00
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Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
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int32_t overflow = (resTemp<63:31> != 0);
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int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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2006-01-29 23:25:54 +01:00
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if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
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else rd.udw = resTemp;}},
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{{0}},
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{{overflow || underflow}},
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{{0}},
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|
{{0}}
|
|
|
|
|
);//SDIVcc
|
|
|
|
|
0x20: taddcc({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd = resTemp = Rs1 + val2;
|
2006-03-07 10:33:10 +01:00
|
|
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
2006-01-29 23:25:54 +01:00
|
|
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
|
|
|
|
{{overflow}},
|
|
|
|
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
|
|
|
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
|
|
|
|
);//TADDcc
|
|
|
|
|
0x21: tsubcc({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd = resTemp = Rs1 + val2;
|
2006-03-07 10:33:10 +01:00
|
|
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
2006-01-29 23:25:54 +01:00
|
|
|
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
|
|
|
|
{{overflow}},
|
|
|
|
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
|
|
|
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
|
|
|
|
);//TSUBcc
|
|
|
|
|
0x22: taddcctv({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd = resTemp = Rs1 + val2;
|
2006-03-07 10:33:10 +01:00
|
|
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
2006-01-29 23:25:54 +01:00
|
|
|
if(overflow) throw tag_overflow;}},
|
|
|
|
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
|
|
|
|
{{overflow}},
|
|
|
|
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
|
|
|
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
|
|
|
|
);//TADDccTV
|
|
|
|
|
0x23: tsubcctv({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd = resTemp = Rs1 + val2;
|
2006-03-07 10:33:10 +01:00
|
|
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
2006-01-29 23:25:54 +01:00
|
|
|
if(overflow) throw tag_overflow;}},
|
|
|
|
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
|
|
|
|
{{overflow}},
|
|
|
|
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
|
|
|
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
|
|
|
|
);//TSUBccTV
|
|
|
|
|
0x24: mulscc({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
|
|
|
|
|
int32_t multiplier = Rs1<31:0>;
|
|
|
|
|
int32_t savedLSB = Rs1<0:>;
|
2006-01-29 23:25:54 +01:00
|
|
|
multiplier = multipler<31:1> |
|
|
|
|
|
((xc->regs.MiscRegs.ccrFields.iccFields.n
|
|
|
|
|
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
|
|
|
|
|
if(!xc->regs.MiscRegs.yFields.value<0:>)
|
|
|
|
|
multiplicand = 0;
|
|
|
|
|
Rd = resTemp = multiplicand + multiplier;
|
|
|
|
|
xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
|
|
|
|
|
{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
|
|
|
|
|
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
|
|
|
|
|
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
|
|
|
|
|
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
|
|
|
|
|
);//MULScc
|
|
|
|
|
}
|
|
|
|
|
format IntegerOp
|
|
|
|
|
{
|
|
|
|
|
0x25: decode X {
|
|
|
|
|
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
|
|
|
|
|
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
|
|
|
|
|
}
|
|
|
|
|
0x26: decode X {
|
|
|
|
|
0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
|
|
|
|
|
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
|
|
|
|
|
}
|
|
|
|
|
0x27: decode X {
|
|
|
|
|
0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
|
|
|
|
|
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
|
|
|
|
|
}
|
|
|
|
|
0x28: decode RS1 {
|
|
|
|
|
0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
|
|
|
|
|
0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
|
|
|
|
|
0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
|
|
|
|
|
0x4: rdtick({{
|
|
|
|
|
if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
|
|
|
|
|
xc->regs.MiscRegs.tickFields.npt == 1)
|
|
|
|
|
throw privileged_action;
|
|
|
|
|
Rd = xc->regs.MiscRegs.tick;
|
|
|
|
|
}});//RDTICK
|
|
|
|
|
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
|
|
|
|
|
0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
|
|
|
|
|
0xF: decode I {
|
|
|
|
|
0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
|
|
|
|
|
0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
0x2A: decode RS1 {
|
|
|
|
|
0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
|
|
|
|
|
0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
|
|
|
|
|
0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
|
|
|
|
|
0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
|
|
|
|
|
0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
|
|
|
|
|
0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
|
|
|
|
|
0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
|
|
|
|
|
0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
|
|
|
|
|
0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
|
|
|
|
|
0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
|
|
|
|
|
0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
|
|
|
|
|
0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
|
|
|
|
|
0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
|
|
|
|
|
0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
|
|
|
|
|
0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
|
|
|
|
|
0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
|
|
|
|
|
}
|
|
|
|
|
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
|
|
|
|
|
0x2C: movcc({{
|
|
|
|
|
ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
|
|
|
|
|
switch(ccBank)
|
|
|
|
|
{
|
|
|
|
|
case 0: case 1: case 2: case 3:
|
|
|
|
|
throw fp_disabled;
|
|
|
|
|
break;
|
|
|
|
|
case 5: case 7:
|
|
|
|
|
throw illegal_instruction;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
|
|
|
|
|
Rd = (I ? SIMM11.sdw : RS2);
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
|
|
|
|
|
Rd = (I ? SIMM11.sdw : RS2);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}});//MOVcc
|
|
|
|
|
0x2D: sdivx({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
if(val2 == 0) throw division_by_zero;
|
|
|
|
|
Rd.sdw = Rs1.sdw / val2;
|
|
|
|
|
}});//SDIVX
|
|
|
|
|
0x2E: decode RS1 {
|
|
|
|
|
0x0: IntegerOp::popc({{
|
2006-03-07 10:33:10 +01:00
|
|
|
int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
|
|
|
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
2006-01-29 23:25:54 +01:00
|
|
|
for(unsigned int x = 0; x < 16; x++)
|
|
|
|
|
{
|
|
|
|
|
count += oneBits[val2 & 0xF];
|
|
|
|
|
val2 >> 4;
|
|
|
|
|
}
|
|
|
|
|
}});//POPC
|
|
|
|
|
}
|
|
|
|
|
0x2F: movr({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
switch(RCOND)
|
|
|
|
|
{
|
|
|
|
|
case 0: case 4:
|
|
|
|
|
throw illegal_instruction;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
if(Rs1 == 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if(Rs1 <= 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if(Rs1 = 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
if(Rs1 != 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
if(Rs1 > 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
if(Rs1 >= 0) Rd = val2;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}});//MOVR
|
|
|
|
|
0x30: decode RD {
|
|
|
|
|
0x0: wry({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.y = Rs1 ^ val2;
|
|
|
|
|
}});//WRY
|
|
|
|
|
0x2: wrccr({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.ccr = Rs1 ^ val2;
|
|
|
|
|
}});//WRCCR
|
|
|
|
|
0x3: wrasi({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
|
|
|
|
}});//WRASI
|
|
|
|
|
0x6: wrfprs({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
|
|
|
|
}});//WRFPRS
|
|
|
|
|
0xF: Trap::sir({{software_initiated_reset}}); //SIR
|
|
|
|
|
}
|
|
|
|
|
0x31: decode FCN {
|
|
|
|
|
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
|
|
|
|
|
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
|
|
|
|
|
}
|
|
|
|
|
0x32: decode RD {
|
|
|
|
|
0x0: wrprtpc({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x1: wrprtnpc({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x2: wrprtstate({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x3: wrprtt({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x4: wrprtick({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tick = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x5: wrprtba({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tba = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x6: wrprpstate({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x7: wrprtl({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.tl = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x8: wrprpil({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.pil = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0x9: wrprcwp({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0xA: wrprcansave({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0xB: wrprcanrestore({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0xC: wrprcleanwin({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0xD: wrprotherwin({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
0xE: wrprwstate({{checkPriv
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
2006-01-29 23:25:54 +01:00
|
|
|
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
|
|
|
|
|
}});
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
|
|
|
|
|
0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x38: Branch::jmpl({{//Stuff}}); //JMPL
|
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|
|
0x39: Branch::return({{//Other Stuff}}); //RETURN
|
|
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|
|
0x3A: Trap::tcc({{
|
|
|
|
|
switch((CC14 << 1) | (CC04 << 0))
|
|
|
|
|
{
|
|
|
|
|
case 1: case 3:
|
|
|
|
|
throw illegal_instruction;
|
|
|
|
|
case 0:
|
|
|
|
|
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
|
|
|
|
|
throw trap_instruction;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
|
|
|
|
|
throw trap_instruction;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}}); //Tcc
|
|
|
|
|
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
|
|
|
|
|
0x3C: BasicOperate::save({{//leprechauns); //SAVE
|
|
|
|
|
0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
|
|
|
|
|
0x3E: decode FCN {
|
|
|
|
|
0x1: BasicOperate::done({{//Done thing}}); //DONE
|
|
|
|
|
0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
0x3: decode OP3 {
|
|
|
|
|
format Mem {
|
|
|
|
|
0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
|
|
|
|
|
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
|
|
|
|
|
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
|
|
|
|
|
0x03: ldd({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val = Mem.udw;
|
2006-01-29 23:25:54 +01:00
|
|
|
setIntReg(RD & (~1), val<31:0>);
|
|
|
|
|
setIntReg(RD | 1, val<63:32>);
|
|
|
|
|
}});//LDD
|
|
|
|
|
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
|
|
|
|
|
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
|
|
|
|
|
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
|
|
|
|
|
0x07: std({{
|
|
|
|
|
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
|
|
|
|
}});//STD
|
|
|
|
|
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
|
|
|
|
|
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
|
|
|
|
|
0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
|
|
|
|
|
0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
|
|
|
|
|
|
|
|
|
|
0x0D: ldstub({{
|
|
|
|
|
Rd.ub = Mem.ub;
|
|
|
|
|
Mem.ub = 0xFF;
|
|
|
|
|
}}); //LDSTUB
|
|
|
|
|
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
|
|
|
|
|
0x0F: swap({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint32_t temp = Rd.uw;
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd.uw = Mem.uw;
|
|
|
|
|
Mem.uw = temp;
|
|
|
|
|
}}); //SWAP
|
|
|
|
|
0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
|
|
|
|
|
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
|
|
|
|
|
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
|
|
|
|
|
0x13: ldda({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint64_t val = Mem.udw;
|
2006-01-29 23:25:54 +01:00
|
|
|
setIntReg(RD & (~1), val<31:0>);
|
|
|
|
|
setIntReg(RD | 1, val<63:32>);
|
|
|
|
|
}}); //LDDA
|
|
|
|
|
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
|
|
|
|
|
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
|
|
|
|
|
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
|
|
|
|
|
0x17: stda({{
|
|
|
|
|
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
|
|
|
|
}}); //STDA
|
|
|
|
|
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
|
|
|
|
|
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
|
|
|
|
|
0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
|
|
|
|
|
0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
|
|
|
|
|
|
|
|
|
|
0x1D: ldstuba({{
|
|
|
|
|
Rd.ub = Mem.ub;
|
|
|
|
|
Mem.ub = 0xFF;
|
|
|
|
|
}}); //LDSTUBA
|
|
|
|
|
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
|
|
|
|
|
0x1F: swapa({{
|
2006-03-07 10:33:10 +01:00
|
|
|
uint32_t temp = Rd.uw;
|
2006-01-29 23:25:54 +01:00
|
|
|
Rd.uw = Mem.uw;
|
|
|
|
|
Mem.uw = temp;
|
|
|
|
|
}}); //SWAPA
|
|
|
|
|
0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
|
|
|
|
|
0x21: decode X {
|
|
|
|
|
0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
|
|
|
|
|
0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
|
|
|
|
|
}
|
|
|
|
|
0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
|
|
|
|
|
0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
|
|
|
|
|
0x24: Trap::stf({{throw fp_disabled;}}); //STF
|
|
|
|
|
0x25: decode X {
|
|
|
|
|
0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
|
|
|
|
|
0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
|
|
|
|
|
}
|
|
|
|
|
0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
|
|
|
|
|
0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x2D: Noop::prefetch({{ }}); //PREFETCH
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
|
|
|
|
|
|
|
|
|
|
0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
|
|
|
|
|
0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
|
|
|
|
|
0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
|
|
|
|
|
0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
|
|
|
|
|
0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x3C: Cas::casa(
|
2006-03-07 10:33:10 +01:00
|
|
|
{{uint64_t val = Mem.uw;
|
2006-01-29 23:25:54 +01:00
|
|
|
if(Rs2.uw == val)
|
|
|
|
|
Mem.uw = Rd.uw;
|
|
|
|
|
Rd.uw = val;
|
|
|
|
|
}}); //CASA
|
|
|
|
|
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
|
|
|
|
0x3E: Cas::casxa(
|
2006-03-07 10:33:10 +01:00
|
|
|
{{uint64_t val = Mem.udw;
|
2006-01-29 23:25:54 +01:00
|
|
|
if(Rs2 == val)
|
|
|
|
|
Mem.udw = Rd;
|
|
|
|
|
Rd = val;
|
|
|
|
|
}}); //CASXA
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
