2004-03-12 17:04:58 +01:00
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/*
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2004-06-04 19:43:50 +02:00
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* Copyright (c) 2004 The Regents of The University of Michigan
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2004-03-12 17:04:58 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2005-06-05 07:22:21 +02:00
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/** @file
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2004-03-12 17:04:58 +01:00
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* Device module for modelling the National Semiconductor
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* DP83820 ethernet controller
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*/
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2004-10-23 22:18:44 +02:00
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#ifndef __DEV_NS_GIGE_HH__
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#define __DEV_NS_GIGE_HH__
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2004-03-12 17:04:58 +01:00
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2004-10-23 22:18:44 +02:00
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#include "base/inet.hh"
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2004-07-27 05:10:20 +02:00
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#include "base/statistics.hh"
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2004-03-12 17:04:58 +01:00
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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2004-07-27 05:10:20 +02:00
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#include "dev/io_device.hh"
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2004-03-12 17:04:58 +01:00
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#include "dev/ns_gige_reg.h"
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#include "dev/pcidev.hh"
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2004-11-13 22:52:08 +01:00
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#include "dev/pktfifo.hh"
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2004-04-22 00:23:41 +02:00
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#include "mem/bus/bus.hh"
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2004-07-27 05:10:20 +02:00
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#include "sim/eventq.hh"
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2004-03-12 17:04:58 +01:00
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/**
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* Ethernet device registers
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*/
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struct dp_regs {
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uint32_t command;
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uint32_t config;
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uint32_t mear;
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uint32_t ptscr;
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uint32_t isr;
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uint32_t imr;
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uint32_t ier;
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uint32_t ihr;
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uint32_t txdp;
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uint32_t txdp_hi;
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uint32_t txcfg;
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uint32_t gpior;
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uint32_t rxdp;
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uint32_t rxdp_hi;
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uint32_t rxcfg;
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uint32_t pqcr;
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uint32_t wcsr;
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uint32_t pcr;
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uint32_t rfcr;
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uint32_t rfdr;
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uint32_t srr;
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uint32_t mibc;
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uint32_t vrcr;
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uint32_t vtcr;
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uint32_t vdr;
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uint32_t ccsr;
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uint32_t tbicr;
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uint32_t tbisr;
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uint32_t tanar;
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uint32_t tanlpar;
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uint32_t taner;
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uint32_t tesr;
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2004-04-22 00:23:41 +02:00
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};
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2004-03-12 17:04:58 +01:00
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2004-04-22 00:23:41 +02:00
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struct dp_rom {
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2004-07-27 05:10:20 +02:00
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/**
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* for perfect match memory.
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* the linux driver doesn't use any other ROM
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*/
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2004-10-23 22:18:44 +02:00
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uint8_t perfectMatch[ETH_ADDR_LEN];
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2004-03-12 17:04:58 +01:00
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};
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2004-05-25 21:59:54 +02:00
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class NSGigEInt;
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2004-03-12 17:04:58 +01:00
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class PhysicalMemory;
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2004-04-22 00:23:41 +02:00
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class BaseInterface;
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class HierParams;
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class Bus;
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class PciConfigAll;
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2004-03-12 17:04:58 +01:00
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/**
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* NS DP82830 Ethernet device model
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*/
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2004-05-25 21:59:54 +02:00
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class NSGigE : public PciDev
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2004-03-12 17:04:58 +01:00
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{
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2004-04-22 00:23:41 +02:00
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public:
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/** Transmit State Machine states */
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enum TxState
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{
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txIdle,
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txDescRefr,
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txDescRead,
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txFifoBlock,
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txFragRead,
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txDescWrite,
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txAdvance
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};
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/** Receive State Machine States */
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enum RxState
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{
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rxIdle,
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rxDescRefr,
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rxDescRead,
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rxFifoBlock,
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rxFragWrite,
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rxDescWrite,
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rxAdvance
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};
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enum DmaState
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{
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dmaIdle,
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dmaReading,
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dmaWriting,
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dmaReadWaiting,
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dmaWriteWaiting
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};
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private:
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2004-03-12 17:04:58 +01:00
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Addr addr;
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2004-04-22 00:23:41 +02:00
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static const Addr size = sizeof(dp_regs);
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protected:
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typedef std::deque<PacketPtr> pktbuf_t;
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typedef pktbuf_t::iterator pktiter_t;
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2004-03-12 17:04:58 +01:00
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/** device register file */
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dp_regs regs;
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2004-04-22 00:23:41 +02:00
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dp_rom rom;
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2004-03-12 17:04:58 +01:00
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2004-06-12 20:24:20 +02:00
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/** pci settings */
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l
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
2004-06-21 23:25:18 +02:00
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bool ioEnable;
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2004-06-12 20:24:20 +02:00
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#if 0
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l
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
2004-06-21 23:25:18 +02:00
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bool memEnable;
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bool bmEnable;
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2004-06-12 20:24:20 +02:00
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#endif
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2004-06-11 21:26:21 +02:00
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/*** BASIC STRUCTURES FOR TX/RX ***/
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2004-03-12 17:04:58 +01:00
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/* Data FIFOs */
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2004-11-13 22:52:08 +01:00
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PacketFifo txFifo;
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PacketFifo rxFifo;
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2004-03-12 17:04:58 +01:00
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/** various helper vars */
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2004-06-11 21:26:21 +02:00
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PacketPtr txPacket;
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PacketPtr rxPacket;
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2004-03-12 17:04:58 +01:00
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uint8_t *txPacketBufPtr;
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uint8_t *rxPacketBufPtr;
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2004-04-22 00:23:41 +02:00
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uint32_t txXferLen;
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uint32_t rxXferLen;
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bool rxDmaFree;
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bool txDmaFree;
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2004-03-12 17:04:58 +01:00
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/** DescCaches */
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ns_desc txDescCache;
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ns_desc rxDescCache;
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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/* state machine cycle time */
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2005-06-02 03:44:00 +02:00
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Tick clock;
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inline Tick cycles(int numCycles) const { return numCycles * clock; }
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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2004-03-12 17:04:58 +01:00
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|
/* tx State Machine */
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2004-04-22 00:23:41 +02:00
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|
|
TxState txState;
|
2004-07-30 17:29:45 +02:00
|
|
|
bool txEnable;
|
|
|
|
|
|
2004-03-12 17:04:58 +01:00
|
|
|
/** Current Transmit Descriptor Done */
|
|
|
|
|
bool CTDD;
|
2004-04-22 00:23:41 +02:00
|
|
|
/** halt the tx state machine after next packet */
|
2004-03-12 17:04:58 +01:00
|
|
|
bool txHalt;
|
2004-04-22 00:23:41 +02:00
|
|
|
/** ptr to the next byte in the current fragment */
|
|
|
|
|
Addr txFragPtr;
|
|
|
|
|
/** count of bytes remaining in the current descriptor */
|
|
|
|
|
uint32_t txDescCnt;
|
|
|
|
|
DmaState txDmaState;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
/** rx State Machine */
|
2004-04-22 00:23:41 +02:00
|
|
|
RxState rxState;
|
2004-07-30 17:29:45 +02:00
|
|
|
bool rxEnable;
|
|
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
/** Current Receive Descriptor Done */
|
|
|
|
|
bool CRDD;
|
|
|
|
|
/** num of bytes in the current packet being drained from rxDataFifo */
|
|
|
|
|
uint32_t rxPktBytes;
|
|
|
|
|
/** halt the rx state machine after current packet */
|
2004-03-12 17:04:58 +01:00
|
|
|
bool rxHalt;
|
2004-04-22 00:23:41 +02:00
|
|
|
/** ptr to the next byte in current fragment */
|
|
|
|
|
Addr rxFragPtr;
|
|
|
|
|
/** count of bytes remaining in the current descriptor */
|
|
|
|
|
uint32_t rxDescCnt;
|
|
|
|
|
DmaState rxDmaState;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
bool extstsEnable;
|
|
|
|
|
|
|
|
|
|
protected:
|
2004-04-22 00:23:41 +02:00
|
|
|
Tick dmaReadDelay;
|
|
|
|
|
Tick dmaWriteDelay;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
Tick dmaReadFactor;
|
|
|
|
|
Tick dmaWriteFactor;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void *rxDmaData;
|
|
|
|
|
Addr rxDmaAddr;
|
|
|
|
|
int rxDmaLen;
|
|
|
|
|
bool doRxDmaRead();
|
|
|
|
|
bool doRxDmaWrite();
|
|
|
|
|
void rxDmaReadCopy();
|
|
|
|
|
void rxDmaWriteCopy();
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void *txDmaData;
|
|
|
|
|
Addr txDmaAddr;
|
|
|
|
|
int txDmaLen;
|
|
|
|
|
bool doTxDmaRead();
|
|
|
|
|
bool doTxDmaWrite();
|
|
|
|
|
void txDmaReadCopy();
|
|
|
|
|
void txDmaWriteCopy();
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void rxDmaReadDone();
|
2004-05-25 21:59:54 +02:00
|
|
|
friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
|
|
|
|
|
EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void rxDmaWriteDone();
|
2004-05-25 21:59:54 +02:00
|
|
|
friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
|
|
|
|
|
EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void txDmaReadDone();
|
2004-05-25 21:59:54 +02:00
|
|
|
friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
|
|
|
|
|
EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void txDmaWriteDone();
|
2004-05-25 21:59:54 +02:00
|
|
|
friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
|
|
|
|
|
EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
|
2004-04-22 00:23:41 +02:00
|
|
|
|
|
|
|
|
bool dmaDescFree;
|
|
|
|
|
bool dmaDataFree;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
protected:
|
|
|
|
|
Tick txDelay;
|
|
|
|
|
Tick rxDelay;
|
|
|
|
|
|
|
|
|
|
void txReset();
|
|
|
|
|
void rxReset();
|
2004-06-11 21:26:21 +02:00
|
|
|
void regsReset();
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
void rxKick();
|
2004-04-22 00:23:41 +02:00
|
|
|
Tick rxKickTick;
|
2004-05-25 21:59:54 +02:00
|
|
|
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
|
2005-01-15 00:34:56 +01:00
|
|
|
friend void RxKickEvent::process();
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
void txKick();
|
|
|
|
|
Tick txKickTick;
|
2004-05-25 21:59:54 +02:00
|
|
|
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
|
2005-01-15 00:34:56 +01:00
|
|
|
friend void TxKickEvent::process();
|
2004-04-22 00:23:41 +02:00
|
|
|
|
|
|
|
|
/**
|
2004-03-12 17:04:58 +01:00
|
|
|
* Retransmit event
|
|
|
|
|
*/
|
2004-04-22 00:23:41 +02:00
|
|
|
void transmit();
|
2004-07-23 18:19:27 +02:00
|
|
|
void txEventTransmit()
|
|
|
|
|
{
|
|
|
|
|
transmit();
|
|
|
|
|
if (txState == txFifoBlock)
|
|
|
|
|
txKick();
|
|
|
|
|
}
|
|
|
|
|
typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
|
2005-01-15 00:34:56 +01:00
|
|
|
friend void TxEvent::process();
|
2004-03-12 17:04:58 +01:00
|
|
|
TxEvent txEvent;
|
|
|
|
|
|
|
|
|
|
void txDump() const;
|
|
|
|
|
void rxDump() const;
|
|
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
/**
|
|
|
|
|
* receive address filter
|
|
|
|
|
*/
|
2004-03-12 17:04:58 +01:00
|
|
|
bool rxFilterEnable;
|
2004-11-13 22:33:16 +01:00
|
|
|
bool rxFilter(const PacketPtr &packet);
|
2004-03-12 17:04:58 +01:00
|
|
|
bool acceptBroadcast;
|
|
|
|
|
bool acceptMulticast;
|
|
|
|
|
bool acceptUnicast;
|
|
|
|
|
bool acceptPerfect;
|
|
|
|
|
bool acceptArp;
|
|
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
PhysicalMemory *physmem;
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Interrupt management
|
|
|
|
|
*/
|
|
|
|
|
void devIntrPost(uint32_t interrupts);
|
|
|
|
|
void devIntrClear(uint32_t interrupts);
|
|
|
|
|
void devIntrChangeMask();
|
|
|
|
|
|
|
|
|
|
Tick intrDelay;
|
|
|
|
|
Tick intrTick;
|
|
|
|
|
bool cpuPendingIntr;
|
|
|
|
|
void cpuIntrPost(Tick when);
|
|
|
|
|
void cpuInterrupt();
|
|
|
|
|
void cpuIntrClear();
|
|
|
|
|
|
2004-05-25 21:59:54 +02:00
|
|
|
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
|
2005-01-15 00:34:56 +01:00
|
|
|
friend void IntrEvent::process();
|
2004-04-22 00:23:41 +02:00
|
|
|
IntrEvent *intrEvent;
|
2004-05-25 21:59:54 +02:00
|
|
|
NSGigEInt *interface;
|
2004-04-22 00:23:41 +02:00
|
|
|
|
2004-03-12 17:04:58 +01:00
|
|
|
public:
|
2004-11-13 21:45:22 +01:00
|
|
|
struct Params : public PciDev::Params
|
|
|
|
|
{
|
|
|
|
|
PhysicalMemory *pmem;
|
|
|
|
|
HierParams *hier;
|
|
|
|
|
Bus *header_bus;
|
|
|
|
|
Bus *payload_bus;
|
2005-06-02 03:44:00 +02:00
|
|
|
Tick clock;
|
2004-11-13 21:45:22 +01:00
|
|
|
Tick intr_delay;
|
|
|
|
|
Tick tx_delay;
|
|
|
|
|
Tick rx_delay;
|
|
|
|
|
Tick pio_latency;
|
|
|
|
|
bool dma_desc_free;
|
|
|
|
|
bool dma_data_free;
|
|
|
|
|
Tick dma_read_delay;
|
|
|
|
|
Tick dma_write_delay;
|
|
|
|
|
Tick dma_read_factor;
|
|
|
|
|
Tick dma_write_factor;
|
|
|
|
|
bool rx_filter;
|
|
|
|
|
Net::EthAddr eaddr;
|
|
|
|
|
uint32_t tx_fifo_size;
|
|
|
|
|
uint32_t rx_fifo_size;
|
2005-04-25 03:32:32 +02:00
|
|
|
uint32_t m5reg;
|
2005-04-30 03:01:43 +02:00
|
|
|
bool dma_no_allocate;
|
2004-11-13 21:45:22 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
NSGigE(Params *params);
|
2004-05-25 21:59:54 +02:00
|
|
|
~NSGigE();
|
2004-11-13 21:45:22 +01:00
|
|
|
const Params *params() const { return (const Params *)_params; }
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
virtual void WriteConfig(int offset, int size, uint32_t data);
|
|
|
|
|
virtual void ReadConfig(int offset, int size, uint8_t *data);
|
|
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
|
|
|
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
bool cpuIntrPending() const;
|
|
|
|
|
void cpuIntrAck() { cpuIntrClear(); }
|
|
|
|
|
|
2004-11-13 22:33:16 +01:00
|
|
|
bool recvPacket(PacketPtr packet);
|
2004-03-12 17:04:58 +01:00
|
|
|
void transferDone();
|
|
|
|
|
|
2004-05-25 21:59:54 +02:00
|
|
|
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
virtual void serialize(std::ostream &os);
|
|
|
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
void regStats();
|
|
|
|
|
|
|
|
|
|
private:
|
2004-05-21 19:39:20 +02:00
|
|
|
Stats::Scalar<> txBytes;
|
|
|
|
|
Stats::Scalar<> rxBytes;
|
|
|
|
|
Stats::Scalar<> txPackets;
|
|
|
|
|
Stats::Scalar<> rxPackets;
|
2004-09-20 16:43:53 +02:00
|
|
|
Stats::Scalar<> txIpChecksums;
|
|
|
|
|
Stats::Scalar<> rxIpChecksums;
|
|
|
|
|
Stats::Scalar<> txTcpChecksums;
|
|
|
|
|
Stats::Scalar<> rxTcpChecksums;
|
|
|
|
|
Stats::Scalar<> txUdpChecksums;
|
|
|
|
|
Stats::Scalar<> rxUdpChecksums;
|
2004-07-04 22:47:07 +02:00
|
|
|
Stats::Scalar<> descDmaReads;
|
|
|
|
|
Stats::Scalar<> descDmaWrites;
|
|
|
|
|
Stats::Scalar<> descDmaRdBytes;
|
|
|
|
|
Stats::Scalar<> descDmaWrBytes;
|
2005-01-20 00:40:02 +01:00
|
|
|
Stats::Formula totBandwidth;
|
|
|
|
|
Stats::Formula totPackets;
|
|
|
|
|
Stats::Formula totBytes;
|
|
|
|
|
Stats::Formula totPacketRate;
|
2004-05-21 19:39:20 +02:00
|
|
|
Stats::Formula txBandwidth;
|
|
|
|
|
Stats::Formula rxBandwidth;
|
|
|
|
|
Stats::Formula txPacketRate;
|
|
|
|
|
Stats::Formula rxPacketRate;
|
2004-11-18 21:46:01 +01:00
|
|
|
Stats::Scalar<> postedSwi;
|
|
|
|
|
Stats::Formula coalescedSwi;
|
|
|
|
|
Stats::Scalar<> totalSwi;
|
|
|
|
|
Stats::Scalar<> postedRxIdle;
|
|
|
|
|
Stats::Formula coalescedRxIdle;
|
|
|
|
|
Stats::Scalar<> totalRxIdle;
|
|
|
|
|
Stats::Scalar<> postedRxOk;
|
|
|
|
|
Stats::Formula coalescedRxOk;
|
|
|
|
|
Stats::Scalar<> totalRxOk;
|
|
|
|
|
Stats::Scalar<> postedRxDesc;
|
|
|
|
|
Stats::Formula coalescedRxDesc;
|
|
|
|
|
Stats::Scalar<> totalRxDesc;
|
|
|
|
|
Stats::Scalar<> postedTxOk;
|
|
|
|
|
Stats::Formula coalescedTxOk;
|
|
|
|
|
Stats::Scalar<> totalTxOk;
|
|
|
|
|
Stats::Scalar<> postedTxIdle;
|
|
|
|
|
Stats::Formula coalescedTxIdle;
|
|
|
|
|
Stats::Scalar<> totalTxIdle;
|
|
|
|
|
Stats::Scalar<> postedTxDesc;
|
|
|
|
|
Stats::Formula coalescedTxDesc;
|
|
|
|
|
Stats::Scalar<> totalTxDesc;
|
|
|
|
|
Stats::Scalar<> postedRxOrn;
|
|
|
|
|
Stats::Formula coalescedRxOrn;
|
|
|
|
|
Stats::Scalar<> totalRxOrn;
|
|
|
|
|
Stats::Formula coalescedTotal;
|
|
|
|
|
Stats::Scalar<> postedInterrupts;
|
|
|
|
|
Stats::Scalar<> droppedPackets;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
2004-04-22 00:23:41 +02:00
|
|
|
public:
|
|
|
|
|
Tick cacheAccess(MemReqPtr &req);
|
2004-03-12 17:04:58 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Ethernet Interface for an Ethernet Device
|
|
|
|
|
*/
|
2004-05-25 21:59:54 +02:00
|
|
|
class NSGigEInt : public EtherInt
|
2004-03-12 17:04:58 +01:00
|
|
|
{
|
|
|
|
|
private:
|
2004-05-25 21:59:54 +02:00
|
|
|
NSGigE *dev;
|
2004-03-12 17:04:58 +01:00
|
|
|
|
|
|
|
|
public:
|
2004-05-25 21:59:54 +02:00
|
|
|
NSGigEInt(const std::string &name, NSGigE *d)
|
2004-03-12 17:04:58 +01:00
|
|
|
: EtherInt(name), dev(d) { dev->setInterface(this); }
|
|
|
|
|
|
2004-11-13 22:33:16 +01:00
|
|
|
virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
|
2004-03-12 17:04:58 +01:00
|
|
|
virtual void sendDone() { dev->transferDone(); }
|
|
|
|
|
};
|
|
|
|
|
|
2004-10-23 22:18:44 +02:00
|
|
|
#endif // __DEV_NS_GIGE_HH__
|
