2007-04-09 09:59:56 +02:00
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|
|
|
|
---------- Begin Simulation Statistics ----------
|
2010-05-14 05:45:59 +02:00
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|
|
host_inst_rate 58626 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 204232 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.25 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 112030496 # Simulator tick rate (ticks/s)
|
2007-04-09 09:59:56 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2008-07-25 01:31:54 +02:00
|
|
|
sim_insts 14449 # Number of instructions simulated
|
2008-08-04 00:13:29 +02:00
|
|
|
sim_seconds 0.000028 # Number of seconds simulated
|
2010-05-14 05:45:59 +02:00
|
|
|
sim_ticks 27640500 # Number of ticks simulated
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 9185 # Number of BTB lookups
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 11479 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.lookups 11479 # Number of BP lookups
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.COM:branches 3359 # Number of branches committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::samples 42520 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::mean 0.356891 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::stdev 0.964493 # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::0-1 34367 80.83% 80.83% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle::1-2 4806 11.30% 92.13% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle::2-3 1719 4.04% 96.17% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle::3-4 713 1.68% 97.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::4-5 414 0.97% 98.82% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::5-6 146 0.34% 99.17% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::6-7 193 0.45% 99.62% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::7-8 48 0.11% 99.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::total 42520 # Number of insts commited each cycle
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.COM:count 15175 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 2226 # Number of loads committed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.COM:refs 3674 # Number of memory references committed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 19910 # The number of squashed insts skipped by commit
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.committedInsts 14449 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.cpi 3.826009 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 3.826009 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35228.070175 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35561.538462 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 3728 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 4016000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.029672 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2311500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 31248.306998 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35612.745098 # average WriteReq mshr miss latency
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 13843000 # number of WriteReq miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3632500 # number of WriteReq MSHR miss cycles
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 32062.836625 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 4727 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 17859000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.105413 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 390 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 5944000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.031605 # mshr miss rate for demand accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.occ_%::0 0.026503 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 108.555093 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 32062.836625 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.overall_hits 4727 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 17859000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.105413 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 557 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 390 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 5944000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.031605 # mshr miss rate for overall accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.tagsinuse 108.555093 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 7141 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 51862 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 20451 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 14795 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 4325 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 11479 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 7330 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 23798 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 830 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 58419 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.207644 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 7330 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 1.056745 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 46845 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 1.247070 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.396969 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::0-1 30399 64.89% 64.89% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1-2 7442 15.89% 80.78% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2-3 1110 2.37% 83.15% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3-4 985 2.10% 85.25% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4-5 1044 2.23% 87.48% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5-6 1211 2.59% 90.07% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6-7 663 1.42% 91.48% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7-8 335 0.72% 92.20% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 3656 7.80% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::total 46845 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 7330 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 33618.691589 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34870.473538 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 6795 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 17986000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.072988 # miss rate for ReadReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 12518500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.048977 # mshr miss rate for ReadReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.avg_refs 18.980447 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_accesses 7330 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 33618.691589 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 6795 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 17986000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.072988 # miss rate for demand accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 12518500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.048977 # mshr miss rate for demand accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.110625 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 226.560324 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 7330 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 33618.691589 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_hits 6795 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 17986000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.072988 # miss rate for overall accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.overall_misses 535 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 12518500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.048977 # mshr miss rate for overall accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 1 # number of replacements
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.tagsinuse 226.560324 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 6795 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.idleCycles 8437 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 4838 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 2088 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.449477 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 2469 # Number of stores executed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:consumers 13103 # num instructions consuming a value
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:fanout 0.824239 # average fanout of values written-back
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:producers 10800 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.432166 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 24095 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 3199 # Number of branch mispredicts detected at execute
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 3043 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 4355 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 24848 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 4325 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 36 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 814 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.261369 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.261369 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 21370 73.18% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 4722 16.17% 89.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 29203 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 44 24.86% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 24.86% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 46845 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623396 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.283288 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 33954 72.48% 72.48% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 5459 11.65% 84.13% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 3016 6.44% 90.57% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 2133 4.55% 95.13% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 995 2.12% 97.25% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 695 1.48% 98.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 336 0.72% 99.45% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 214 0.46% 99.91% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 46845 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.528255 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 32305 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 29203 # Number of instructions issued
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 15689 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 12321 # Number of squashed operands that are examined and possibly removed from graph
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.590361 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2855000 # number of ReadExReq miss cycles
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.761905 # average ReadReq mshr miss latency
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 13022000 # number of ReadReq MSHR miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
|
2007-11-29 09:00:26 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34342.105263 # average UpgradeReq miss latency
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 652500 # number of UpgradeReq miss cycles
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2007-11-29 09:00:26 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2007-11-29 09:00:26 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34248.508946 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 17227000 # number of demand (read+write) miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 15621000 # number of demand (read+write) MSHR miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.007671 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 251.347828 # Average occupied blocks per context
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34248.508946 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 17227000 # number of overall miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 503 # number of overall misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 15621000 # number of overall MSHR miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 251.347828 # Cycle average of tags in use
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 55282 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 22239 # Number of cycles rename is idle
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 74814 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 42611 # Number of instructions processed by rename
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:RunCycles 13163 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 4325 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 6774 # count of cycles rename stalled for serializing inst
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 5153 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 824 # count of temporary serializing insts renamed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
2007-04-09 09:59:56 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
