gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled May  8 2012 15:05:30
gem5 started May  8 2012 15:50:07
gem5 executing on piton
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Hello world!
Exiting @ tick 28768000 because target called exit()
X86 Regressions: Update stats due to fence instruction 2012-01-10 16:59:01 +01:00			`gem5 Simulator System. http://gem5.org`
			`gem5 is copyrighted software; use the --copyright option for details.`
X86: Add x86 reference output for the timing CPU. 2008-11-10 06:57:15 +01:00
stats: update stats for no_value -> nan Lots of accumulated older changes too. 2012-05-09 20:52:14 +02:00			`gem5 compiled May 8 2012 15:05:30`
			`gem5 started May 8 2012 15:50:07`
			`gem5 executing on piton`
			`command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing`
X86: Add x86 reference output for the timing CPU. 2008-11-10 06:57:15 +01:00			`Global frequency set at 1000000000000 ticks per second`
			`info: Entering event queue @ 0. Starting simulation...`
			`Hello world!`
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. 2010-09-09 20:40:19 +02:00			`Exiting @ tick 28768000 because target called exit()`