2006-05-16 23:36:50 +02:00
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Steve Reinhardt
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2006-05-16 23:36:50 +02:00
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*/
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#include "arch/utility.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple/atomic.hh"
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#include "mem/packet_impl.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace TheISA;
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AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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void
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AtomicSimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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AtomicSimpleCPU::TickEvent::description()
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{
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return "AtomicSimpleCPU tick event";
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}
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void
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AtomicSimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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2006-06-06 23:32:21 +02:00
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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2006-05-16 23:36:50 +02:00
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// initialize CPU, including PC
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2006-06-06 23:32:21 +02:00
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TheISA::initCPU(tc, tc->readCpuId());
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2006-05-16 23:36:50 +02:00
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}
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#endif
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}
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bool
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2006-05-19 04:32:21 +02:00
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AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
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2006-05-16 23:36:50 +02:00
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{
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panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
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return true;
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}
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Tick
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2006-05-19 04:32:21 +02:00
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AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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2006-05-16 23:36:50 +02:00
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{
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panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
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return curTick;
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}
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void
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2006-05-19 04:32:21 +02:00
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AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
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2006-05-16 23:36:50 +02:00
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{
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panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
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}
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void
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AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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2006-05-18 04:08:44 +02:00
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if (status == RangeChange)
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return;
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2006-05-16 23:36:50 +02:00
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panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
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}
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2006-05-31 00:57:42 +02:00
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void
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2006-05-16 23:36:50 +02:00
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AtomicSimpleCPU::CpuPort::recvRetry()
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{
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panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
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}
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AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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: BaseSimpleCPU(p), tickEvent(this),
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width(p->width), simulate_stalls(p->simulate_stalls),
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2006-05-26 19:48:35 +02:00
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icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
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2006-05-16 23:36:50 +02:00
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{
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_status = Idle;
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2006-05-31 06:12:29 +02:00
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// @todo fix me and get the real cpu id & thread number!!!
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ifetch_req = new Request();
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2006-05-26 20:17:33 +02:00
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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2006-05-16 23:36:50 +02:00
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ifetch_pkt->dataStatic(&inst);
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2006-05-31 06:12:29 +02:00
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data_read_req = new Request();
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2006-05-26 20:17:33 +02:00
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data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
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Packet::Broadcast);
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2006-05-16 23:36:50 +02:00
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data_read_pkt->dataStatic(&dataReg);
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2006-05-31 06:12:29 +02:00
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data_write_req = new Request();
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2006-05-26 20:17:33 +02:00
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data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
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Packet::Broadcast);
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2006-05-16 23:36:50 +02:00
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}
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AtomicSimpleCPU::~AtomicSimpleCPU()
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{
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}
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void
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AtomicSimpleCPU::serialize(ostream &os)
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{
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SERIALIZE_ENUM(_status);
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2006-06-30 01:45:24 +02:00
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BaseSimpleCPU::serialize(os);
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2006-05-16 23:36:50 +02:00
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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}
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void
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AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_ENUM(_status);
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2006-06-30 01:45:24 +02:00
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BaseSimpleCPU::unserialize(cp, section);
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2006-05-16 23:36:50 +02:00
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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}
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void
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2006-06-30 01:45:24 +02:00
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AtomicSimpleCPU::switchOut()
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2006-05-16 23:36:50 +02:00
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{
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2006-06-30 01:45:24 +02:00
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assert(status() == Running || status() == Idle);
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_status = SwitchedOut;
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2006-05-16 23:36:50 +02:00
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2006-06-30 01:45:24 +02:00
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tickEvent.squash();
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2006-05-16 23:36:50 +02:00
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}
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void
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AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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2006-06-06 23:32:21 +02:00
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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2006-05-16 23:36:50 +02:00
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// running and schedule its tick event.
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2006-06-06 23:32:21 +02:00
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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2006-05-16 23:36:50 +02:00
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_status = Running;
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tickEvent.schedule(curTick);
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break;
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}
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}
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}
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void
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AtomicSimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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2006-06-07 21:29:53 +02:00
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assert(thread);
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2006-05-16 23:36:50 +02:00
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assert(_status == Idle);
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assert(!tickEvent.scheduled());
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notIdleFraction++;
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tickEvent.schedule(curTick + cycles(delay));
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_status = Running;
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}
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void
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AtomicSimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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2006-06-07 21:29:53 +02:00
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assert(thread);
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2006-05-16 23:36:50 +02:00
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assert(_status == Running);
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2006-05-18 04:08:44 +02:00
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// tick event may not be scheduled if this gets called from inside
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// an instruction's execution, e.g. "quiesce"
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if (tickEvent.scheduled())
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tickEvent.deschedule();
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2006-05-16 23:36:50 +02:00
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notIdleFraction--;
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_status = Idle;
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}
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template <class T>
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Fault
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AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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2006-06-07 21:29:53 +02:00
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data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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2006-05-16 23:36:50 +02:00
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if (traceData) {
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traceData->setAddr(addr);
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}
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// translate to physical address
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2006-06-07 21:29:53 +02:00
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Fault fault = thread->translateDataReadReq(data_read_req);
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2006-05-16 23:36:50 +02:00
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// Now do the access.
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if (fault == NoFault) {
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2006-05-26 20:17:33 +02:00
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data_read_pkt->reinitFromRequest();
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2006-05-16 23:36:50 +02:00
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2006-05-31 04:30:42 +02:00
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dcache_latency = dcachePort.sendAtomic(data_read_pkt);
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2006-05-16 23:36:50 +02:00
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dcache_access = true;
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2006-05-26 20:17:33 +02:00
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assert(data_read_pkt->result == Packet::Success);
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2006-05-16 23:36:50 +02:00
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data = data_read_pkt->get<T>();
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}
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// This will need a new way to tell if it has a dcache attached.
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if (data_read_req->getFlags() & UNCACHEABLE)
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recordEvent("Uncached Read");
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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2006-06-07 21:29:53 +02:00
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data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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2006-05-16 23:36:50 +02:00
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if (traceData) {
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traceData->setAddr(addr);
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}
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// translate to physical address
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2006-06-07 21:29:53 +02:00
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Fault fault = thread->translateDataWriteReq(data_write_req);
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2006-05-16 23:36:50 +02:00
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// Now do the access.
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if (fault == NoFault) {
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data = htog(data);
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2006-05-26 20:17:33 +02:00
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data_write_pkt->reinitFromRequest();
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2006-05-31 04:30:42 +02:00
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data_write_pkt->dataStatic(&data);
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2006-05-16 23:36:50 +02:00
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2006-05-31 04:30:42 +02:00
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dcache_latency = dcachePort.sendAtomic(data_write_pkt);
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2006-05-16 23:36:50 +02:00
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dcache_access = true;
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2006-05-26 20:17:33 +02:00
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assert(data_write_pkt->result == Packet::Success);
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2006-05-16 23:36:50 +02:00
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2006-05-19 04:54:19 +02:00
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if (res && data_write_req->getFlags() & LOCKED) {
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*res = data_write_req->getScResult();
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}
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}
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2006-05-16 23:36:50 +02:00
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (data_write_req->getFlags() & UNCACHEABLE)
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recordEvent("Uncached Write");
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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AtomicSimpleCPU::write(uint64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint16_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint8_t data, Addr addr,
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unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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void
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AtomicSimpleCPU::tick()
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{
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Tick latency = cycles(1); // instruction takes one cycle by default
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for (int i = 0; i < width; ++i) {
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numCycles++;
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2006-05-18 04:08:44 +02:00
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checkForInterrupts();
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2006-05-31 04:30:42 +02:00
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Fault fault = setupFetchRequest(ifetch_req);
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2006-05-16 23:36:50 +02:00
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if (fault == NoFault) {
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2006-05-31 04:30:42 +02:00
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ifetch_pkt->reinitFromRequest();
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Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
|
2006-05-16 23:36:50 +02:00
|
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|
// ifetch_req is initialized to read the instruction directly
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|
// into the CPU object's inst field.
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dcache_access = false; // assume no dcache access
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|
preExecute();
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|
fault = curStaticInst->execute(this, traceData);
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|
postExecute();
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|
|
if (simulate_stalls) {
|
2006-05-31 04:30:42 +02:00
|
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|
Tick icache_stall = icache_latency - cycles(1);
|
2006-05-16 23:36:50 +02:00
|
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|
Tick dcache_stall =
|
2006-05-31 04:30:42 +02:00
|
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|
dcache_access ? dcache_latency - cycles(1) : 0;
|
2006-06-26 23:50:48 +02:00
|
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|
Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
|
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|
if (cycles(stall_cycles) < (icache_stall + dcache_stall))
|
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|
latency += cycles(stall_cycles+1);
|
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|
else
|
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|
latency += cycles(stall_cycles);
|
2006-05-16 23:36:50 +02:00
|
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|
}
|
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|
}
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|
advancePC(fault);
|
|
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|
}
|
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|
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|
2006-05-18 04:08:44 +02:00
|
|
|
if (_status != Idle)
|
|
|
|
tickEvent.schedule(curTick + latency);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
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|
////////////////////////////////////////////////////////////////////////
|
|
|
|
//
|
|
|
|
// AtomicSimpleCPU Simulation Object
|
|
|
|
//
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
|
|
|
|
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
|
|
Param<Counter> max_insts_all_threads;
|
|
|
|
Param<Counter> max_loads_any_thread;
|
|
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
SimObjectParam<MemObject *> mem;
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
SimObjectParam<AlphaITB *> itb;
|
|
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
|
|
SimObjectParam<System *> system;
|
|
|
|
Param<int> cpu_id;
|
|
|
|
Param<Tick> profile;
|
|
|
|
#else
|
|
|
|
SimObjectParam<Process *> workload;
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
|
|
|
|
Param<int> clock;
|
|
|
|
|
|
|
|
Param<bool> defer_registration;
|
|
|
|
Param<int> width;
|
|
|
|
Param<bool> function_trace;
|
|
|
|
Param<Tick> function_trace_start;
|
|
|
|
Param<bool> simulate_stalls;
|
|
|
|
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
|
|
|
|
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
|
|
|
|
|
|
|
|
INIT_PARAM(max_insts_any_thread,
|
|
|
|
"terminate when any thread reaches this inst count"),
|
|
|
|
INIT_PARAM(max_insts_all_threads,
|
|
|
|
"terminate when all threads have reached this inst count"),
|
|
|
|
INIT_PARAM(max_loads_any_thread,
|
|
|
|
"terminate when any thread reaches this load count"),
|
|
|
|
INIT_PARAM(max_loads_all_threads,
|
|
|
|
"terminate when all threads have reached this load count"),
|
|
|
|
INIT_PARAM(mem, "memory"),
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
|
|
INIT_PARAM(system, "system object"),
|
|
|
|
INIT_PARAM(cpu_id, "processor ID"),
|
|
|
|
INIT_PARAM(profile, ""),
|
|
|
|
#else
|
|
|
|
INIT_PARAM(workload, "processes to run"),
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
|
|
|
|
INIT_PARAM(clock, "clock speed"),
|
|
|
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
|
|
|
INIT_PARAM(width, "cpu width"),
|
|
|
|
INIT_PARAM(function_trace, "Enable function trace"),
|
|
|
|
INIT_PARAM(function_trace_start, "Cycle to start function trace"),
|
|
|
|
INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
|
|
|
|
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
|
|
|
|
|
|
|
|
|
|
|
|
CREATE_SIM_OBJECT(AtomicSimpleCPU)
|
|
|
|
{
|
|
|
|
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
|
|
|
|
params->name = getInstanceName();
|
|
|
|
params->numberOfThreads = 1;
|
|
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
|
|
params->deferRegistration = defer_registration;
|
|
|
|
params->clock = clock;
|
|
|
|
params->functionTrace = function_trace;
|
|
|
|
params->functionTraceStart = function_trace_start;
|
|
|
|
params->width = width;
|
|
|
|
params->simulate_stalls = simulate_stalls;
|
|
|
|
params->mem = mem;
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
params->itb = itb;
|
|
|
|
params->dtb = dtb;
|
|
|
|
params->system = system;
|
|
|
|
params->cpu_id = cpu_id;
|
|
|
|
params->profile = profile;
|
|
|
|
#else
|
|
|
|
params->process = workload;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
|
|
|
|
return cpu;
|
|
|
|
}
|
|
|
|
|
|
|
|
REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
|
|
|
|
|