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don't depend on the memory system to return the atomic cpu a multiple of cpu cycles.

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--HG--
extra : convert_revision : e5eb36f14c8394381a0269fefd34a178833c8346
This commit is contained in:
Ali Saidi 2006-06-26 17:50:48 -04:00
parent b1cfe01b57
commit 60454042aa
1 changed files with 5 additions and 6 deletions
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11
src/cpu/simple/atomic.cc
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@ -410,15 +410,14 @@ AtomicSimpleCPU::tick()
postExecute();
if (simulate_stalls) {
// This calculation assumes that the icache and dcache
// access latencies are always a multiple of the CPU's
// cycle time. If not, the next tick event may get
// scheduled at a non-integer multiple of the CPU
// cycle time.
Tick icache_stall = icache_latency - cycles(1);
Tick dcache_stall =
dcache_access ? dcache_latency - cycles(1) : 0;
latency += icache_stall + dcache_stall;
Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
if (cycles(stall_cycles) < (icache_stall + dcache_stall))
latency += cycles(stall_cycles+1);
else
latency += cycles(stall_cycles);
}
}