gem5/configs/test/test.py

from m5 import *

class HelloWorld(AlphaLiveProcess):
    executable = '../configs/test/hello'
    cmd = 'hello'

magicbus = Bus()
mem = PhysicalMemory()
cpu = AtomicSimpleCPU(workload=HelloWorld(), mem=magicbus)
system = System(physmem=mem, cpu=cpu)
system.c1 =  Connector(side_a=mem, side_b=magicbus)
root = Root(system=system)
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`from m5 import *`

add translations for new sections that are mmapped or when the brk is changed Add a default machine width parameter Arch based live processes arch/alpha/linux/process.cc: arch/alpha/linux/process.hh: arch/alpha/process.cc: arch/alpha/process.hh: arch/alpha/tru64/process.cc: arch/alpha/tru64/process.hh: arch/mips/linux_process.cc: arch/mips/process.cc: arch/mips/process.hh: arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: arch/sparc/process.cc: arch/sparc/process.hh: configs/test/test.py: python/m5/objects/Process.py: sim/process.cc: sim/process.hh: Architecture based live processes arch/mips/isa_traits.hh: arch/sparc/isa_traits.hh: Add a default machine width parameter mem/port.hh: gcc 4 really wants a virtual destructor sim/byteswap.hh: remove the comment around long and unsigned long even though uint32_t and int32_t are defined. Seems to work with gcc 4 and 3.4.3. sim/syscall_emul.cc: sim/syscall_emul.hh: add translations for new sections that are mmapped or when the brk is changed --HG-- extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6 2006-03-15 23:04:50 +01:00			`class HelloWorld(AlphaLiveProcess):`
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`executable = '../configs/test/hello'`
			`cmd = 'hello'`

update for objects having a bus --HG-- extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b 2006-03-26 00:34:50 +01:00			`magicbus = Bus()`
update for connector magic --HG-- extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58 2006-03-30 00:39:20 +02:00			`mem = PhysicalMemory()`
Split SimpleCPU into two different models, AtomicSimpleCPU and TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132 2006-05-16 23:36:50 +02:00			`cpu = AtomicSimpleCPU(workload=HelloWorld(), mem=magicbus)`
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`system = System(physmem=mem, cpu=cpu)`
update for connector magic --HG-- extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58 2006-03-30 00:39:20 +02:00			`system.c1 = Connector(side_a=mem, side_b=magicbus)`
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`root = Root(system=system)`