gem5/configs/test/test.py

from m5 import *

class HelloWorld(AlphaLiveProcess):
    executable = '../configs/test/hello'
    cmd = 'hello'

magicbus = Bus()
mem = PhysicalMemory(bus=magicbus)
cpu = SimpleCPU(workload=HelloWorld(), mem=magicbus)
system = System(physmem=mem, cpu=cpu)
root = Root(system=system)
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`from m5 import *`

add translations for new sections that are mmapped or when the brk is changed Add a default machine width parameter Arch based live processes arch/alpha/linux/process.cc: arch/alpha/linux/process.hh: arch/alpha/process.cc: arch/alpha/process.hh: arch/alpha/tru64/process.cc: arch/alpha/tru64/process.hh: arch/mips/linux_process.cc: arch/mips/process.cc: arch/mips/process.hh: arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: arch/sparc/process.cc: arch/sparc/process.hh: configs/test/test.py: python/m5/objects/Process.py: sim/process.cc: sim/process.hh: Architecture based live processes arch/mips/isa_traits.hh: arch/sparc/isa_traits.hh: Add a default machine width parameter mem/port.hh: gcc 4 really wants a virtual destructor sim/byteswap.hh: remove the comment around long and unsigned long even though uint32_t and int32_t are defined. Seems to work with gcc 4 and 3.4.3. sim/syscall_emul.cc: sim/syscall_emul.hh: add translations for new sections that are mmapped or when the brk is changed --HG-- extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6 2006-03-15 23:04:50 +01:00			`class HelloWorld(AlphaLiveProcess):`
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`executable = '../configs/test/hello'`
			`cmd = 'hello'`

update for objects having a bus --HG-- extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b 2006-03-26 00:34:50 +01:00			`magicbus = Bus()`
			`mem = PhysicalMemory(bus=magicbus)`
			`cpu = SimpleCPU(workload=HelloWorld(), mem=magicbus)`
Compiles now (with CPU_MODELS=SimpleCPU), but hangs on execution. configs/test/test.py: Move test binary out of m5-test, don't depend on m5-test/Benchmarks. python/m5/objects/System.py: Split out full-system-only parameters (lost in merge). sim/system.cc: Need to be able to instantiate System directly in SE mode (lost in merge). sim/system.hh: A few more functions here are FS-only. configs/test/hello: Add in binary. --HG-- rename : configs/test.py => configs/test/test.py extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395 2006-03-10 16:01:29 +01:00			`system = System(physmem=mem, cpu=cpu)`
			`root = Root(system=system)`