2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2010-09-22 08:07:35 +02:00
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sim_seconds 0.148086 # Number of seconds simulated
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2011-03-18 01:20:22 +01:00
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sim_ticks 148086239000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-02-12 23:07:43 +01:00
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host_inst_rate 1696896 # Simulator instruction rate (inst/s)
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host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2774293546 # Simulator tick rate (ticks/s)
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host_mem_usage 354444 # Number of bytes of host memory used
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host_seconds 53.38 # Real time elapsed on the host
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sim_insts 90576869 # Number of instructions simulated
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sim_ops 91226321 # Number of ops (including micro ops) simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 986112 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 2048 # Number of bytes written to this memory
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system.physmem.num_reads 15408 # Number of read requests responded to by this memory
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system.physmem.num_writes 32 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
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2010-11-08 20:58:25 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 296172478 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-12 23:07:43 +01:00
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system.cpu.committedInsts 90576869 # Number of instructions committed
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system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
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2012-01-25 18:19:50 +01:00
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system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
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system.cpu.num_func_calls 96832 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
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system.cpu.num_int_insts 72525682 # number of integer instructions
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system.cpu.num_fp_insts 48 # number of float instructions
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system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
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system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
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system.cpu.num_mem_refs 27318811 # number of memory refs
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system.cpu.num_load_insts 22573967 # Number of load instructions
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system.cpu.num_store_insts 4744844 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 296172478 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 2 # number of replacements
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system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
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system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
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system.cpu.icache.overall_hits::total 107830181 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
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system.cpu.icache.overall_misses::total 599 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 942702 # number of replacements
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system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits
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system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
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system.cpu.dcache.overall_misses::total 946798 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
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|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 942309 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 634 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 931989 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 15408 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 32 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
