2014-07-28 18:23:23 +02:00
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/*
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2015-07-30 09:41:42 +02:00
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* Copyright (c) 2012-2014 ARM Limited
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2014-07-28 18:23:23 +02:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Definitions of a base set associative tag store.
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*/
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#include <string>
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#include "base/intmath.hh"
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#include "mem/cache/tags/base_set_assoc.hh"
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#include "sim/core.hh"
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using namespace std;
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BaseSetAssoc::BaseSetAssoc(const Params *p)
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2015-07-30 09:41:42 +02:00
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:BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
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2014-07-28 18:23:23 +02:00
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numSets(p->size / (p->block_size * p->assoc)),
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sequentialAccess(p->sequential_access)
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{
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// Check parameters
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if (blkSize < 4 || !isPowerOf2(blkSize)) {
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fatal("Block size must be at least 4 and a power of 2");
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}
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if (numSets <= 0 || !isPowerOf2(numSets)) {
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fatal("# of sets must be non-zero and a power of 2");
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}
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if (assoc <= 0) {
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fatal("associativity must be greater than zero");
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}
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blkMask = blkSize - 1;
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setShift = floorLog2(blkSize);
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setMask = numSets - 1;
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tagShift = setShift + floorLog2(numSets);
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/** @todo Make warmup percentage a parameter. */
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warmupBound = numSets * assoc;
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sets = new SetType[numSets];
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blks = new BlkType[numSets * assoc];
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// allocate data storage in one big chunk
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numBlocks = numSets * assoc;
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dataBlks = new uint8_t[numBlocks * blkSize];
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unsigned blkIndex = 0; // index into blks array
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for (unsigned i = 0; i < numSets; ++i) {
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sets[i].assoc = assoc;
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sets[i].blks = new BlkType*[assoc];
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// link in the data blocks
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for (unsigned j = 0; j < assoc; ++j) {
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// locate next cache block
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BlkType *blk = &blks[blkIndex];
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blk->data = &dataBlks[blkSize*blkIndex];
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++blkIndex;
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// invalidate new cache block
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blk->invalidate();
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//EGH Fix Me : do we need to initialize blk?
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// Setting the tag to j is just to prevent long chains in the hash
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// table; won't matter because the block is invalid
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blk->tag = j;
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blk->whenReady = 0;
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blk->isTouched = false;
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blk->size = blkSize;
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sets[i].blks[j]=blk;
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blk->set = i;
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blk->way = j;
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2014-07-28 18:23:23 +02:00
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}
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}
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}
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BaseSetAssoc::~BaseSetAssoc()
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{
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delete [] dataBlks;
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delete [] blks;
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delete [] sets;
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}
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2015-05-05 09:22:21 +02:00
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CacheBlk*
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BaseSetAssoc::findBlock(Addr addr, bool is_secure) const
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{
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Addr tag = extractTag(addr);
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unsigned set = extractSet(addr);
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BlkType *blk = sets[set].findBlk(tag, is_secure);
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return blk;
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}
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2015-07-30 09:41:42 +02:00
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CacheBlk*
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BaseSetAssoc::findBlockBySetAndWay(int set, int way) const
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{
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return sets[set].blks[way];
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}
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2014-07-28 18:23:23 +02:00
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void
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BaseSetAssoc::clearLocks()
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{
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for (int i = 0; i < numBlocks; i++){
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blks[i].clearLoadLocks();
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}
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}
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std::string
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BaseSetAssoc::print() const {
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std::string cache_state;
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for (unsigned i = 0; i < numSets; ++i) {
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// link in the data blocks
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for (unsigned j = 0; j < assoc; ++j) {
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BlkType *blk = sets[i].blks[j];
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if (blk->isValid())
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cache_state += csprintf("\tset: %d block: %d %s\n", i, j,
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blk->print());
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}
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}
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if (cache_state.empty())
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cache_state = "no valid tags\n";
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return cache_state;
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}
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void
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BaseSetAssoc::cleanupRefs()
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{
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for (unsigned i = 0; i < numSets*assoc; ++i) {
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if (blks[i].isValid()) {
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totalRefs += blks[i].refCount;
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++sampledRefs;
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}
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}
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}
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void
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BaseSetAssoc::computeStats()
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{
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for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) {
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occupanciesTaskId[i] = 0;
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for (unsigned j = 0; j < 5; ++j) {
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ageTaskId[i][j] = 0;
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}
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}
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for (unsigned i = 0; i < numSets * assoc; ++i) {
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if (blks[i].isValid()) {
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assert(blks[i].task_id < ContextSwitchTaskId::NumTaskId);
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occupanciesTaskId[blks[i].task_id]++;
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2014-09-19 16:35:07 +02:00
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assert(blks[i].tickInserted <= curTick());
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Tick age = curTick() - blks[i].tickInserted;
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int age_index;
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if (age / SimClock::Int::us < 10) { // <10us
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age_index = 0;
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} else if (age / SimClock::Int::us < 100) { // <100us
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age_index = 1;
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} else if (age / SimClock::Int::ms < 1) { // <1ms
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age_index = 2;
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} else if (age / SimClock::Int::ms < 10) { // <10ms
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age_index = 3;
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} else
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age_index = 4; // >10ms
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ageTaskId[blks[i].task_id][age_index]++;
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}
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}
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}
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