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gem5/src/mem/cache
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David Guillen-Fandos 0c89c15b23 mem: Make caches way aware 
This patch makes cache sets aware of the way number. This enables
some nice features such as the ablity to restrict way allocation. The
implemented mechanism allows to set a maximum way number to be
allocated 'k' which must fulfill 0 < k <= N (where N is the number of
ways). In the future more sophisticated mechasims can be implemented.
2015-07-30 03:41:42 -04:00
..
prefetch mem: Fix (ab)use of emplace to avoid temporary object creation 2015-07-13 08:46:28 -04:00
tags mem: Make caches way aware 2015-07-30 03:41:42 -04:00
base.cc sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
base.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
BaseCache.py mem: Remove redundant is_top_level cache parameter 2015-07-03 10:14:43 -04:00
blk.cc mem: Add support for a security bit in the memory system 2014-01-24 15:29:30 -06:00
blk.hh mem: Make caches way aware 2015-07-30 03:41:42 -04:00
cache.cc mem: Remove templates in cache model 2015-05-05 03:22:21 -04:00
cache.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
cache_impl.hh mem: Make caches way aware 2015-07-30 03:41:42 -04:00
mshr.cc mem: Fix (ab)use of emplace to avoid temporary object creation 2015-07-13 08:46:28 -04:00
mshr.hh mem: Modernise MSHR iterators to C++11 2015-03-27 04:55:57 -04:00
mshr_queue.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
mshr_queue.hh sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
SConscript arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00