gem5/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                         2711                       # Number of BTB hits
global.BPredUnit.BTBLookups                      6964                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                       0                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                   2012                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted                   7659                       # Number of conditional branches predicted
global.BPredUnit.lookups                         7659                       # Number of BP lookups
global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
host_inst_rate                                   2546                       # Simulator instruction rate (inst/s)
host_mem_usage                                 181644                       # Number of bytes of host memory used
host_seconds                                     4.09                       # Real time elapsed on the host
host_tick_rate                                3665441                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads                 15                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads                  3077                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores                 2956                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                       10411                       # Number of instructions simulated
sim_seconds                                  0.000015                       # Number of seconds simulated
sim_ticks                                    14990500                       # Number of ticks simulated
system.cpu.commit.COM:branches                   2152                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events                87                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples        26989                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0        21416   7935.08%           
                               1         3114   1153.80%           
                               2         1160    429.80%           
                               3          589    218.24%           
                               4          306    113.38%           
                               5           84     31.12%           
                               6          196     72.62%           
                               7           37     13.71%           
                               8           87     32.24%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                     10976                       # Number of instructions committed
system.cpu.commit.COM:loads                      1462                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                       2760                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts              2012                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts          10976                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls             329                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts           13198                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                       10411                       # Number of Instructions Simulated
system.cpu.committedInsts_total                 10411                       # Number of Instructions Simulated
system.cpu.cpi                               2.879839                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.879839                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               2274                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency  9734.848485                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5560.606061                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   2208                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency         642500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.029024                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   66                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                25                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency       367000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.029024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              66                       # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses              1171                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 16414.285714                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency  5623.809524                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                  1066                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       1723500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.089667                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 105                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits              121                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency       590500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.089667                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses            105                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  21.703947                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                3445                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13836.257310                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  5599.415205                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    3274                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         2366000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.049637                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   171                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                146                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency       957500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.049637                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              171                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses               3445                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13836.257310                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  5599.415205                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   3274                       # number of overall hits
system.cpu.dcache.overall_miss_latency        2366000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.049637                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  171                       # number of overall misses
system.cpu.dcache.overall_mshr_hits               146                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency       957500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.049637                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             171                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    152                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                111.288485                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     3299                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles           3945                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts           38084                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles             12820                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles              10159                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles            2909                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles             65                       # Number of cycles decode is unblocking
system.cpu.fetch.Branches                        7659                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                      4927                       # Number of cache lines fetched
system.cpu.fetch.Cycles                         16219                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                   589                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                          42202                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                    2099                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.255453                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles               4927                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches               2711                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.407578                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples               29898                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0        18628   6230.52%           
                               1         4885   1633.89%           
                               2          619    207.04%           
                               3          712    238.14%           
                               4          788    263.56%           
                               5          640    214.06%           
                               6          611    204.36%           
                               7          195     65.22%           
                               8         2820    943.21%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses               4907                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency  7495.945946                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  5325.675676                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   4537                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        2773500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.075402                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  370                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                20                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency      1970500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.075402                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             370                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  12.262162                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                4907                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency  7495.945946                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  5325.675676                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    4537                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         2773500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.075402                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   370                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 20                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      1970500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.075402                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              370                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses               4907                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency  7495.945946                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  5325.675676                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   4537                       # number of overall hits
system.cpu.icache.overall_miss_latency        2773500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.075402                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  370                       # number of overall misses
system.cpu.icache.overall_mshr_hits                20                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency      1970500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.075402                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             370                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements                      1                       # number of replacements
system.cpu.icache.sampled_refs                    370                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                233.477311                       # Cycle average of tags in use
system.cpu.icache.total_refs                     4537                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                              84                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                     3086                       # Number of branches executed
system.cpu.iew.EXEC:nop                          1794                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     0.575379                       # Inst execution rate
system.cpu.iew.EXEC:refs                         4543                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                       2116                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                      9189                       # num instructions consuming a value
system.cpu.iew.WB:count                         16618                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.827620                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                      7605                       # num instructions producing a value
system.cpu.iew.WB:rate                       0.554266                       # insts written-back per cycle
system.cpu.iew.WB:sent                          16830                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts                 2216                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                       0                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts                  3077                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                612                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts              2973                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts                 2956                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts               24330                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts                  2427                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts              2838                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts                 17251                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles                   2909                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                     0                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads              46                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation           57                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads         1615                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores         1658                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents             57                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect          695                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect           1521                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               0.347242                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.347242                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0                   20089                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass            0      0.00%            # Type of FU issued
                          IntAlu        14535     72.35%            # Type of FU issued
                         IntMult            0      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            0      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead         2907     14.47%            # Type of FU issued
                        MemWrite         2647     13.18%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt                   188                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.009358                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu           50     26.60%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead           23     12.23%            # attempts to use FU when none available
                        MemWrite          115     61.17%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples        29898                      
system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0        21040   7037.26%           
                               1         3621   1211.12%           
                               2         2127    711.42%           
                               3         1561    522.11%           
                               4          748    250.18%           
                               5          407    136.13%           
                               6          293     98.00%           
                               7           62     20.74%           
                               8           39     13.04%           
system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle.end_dist

system.cpu.iq.ISSUE:rate                     0.670035                       # Inst issue rate
system.cpu.iq.iqInstsAdded                      21924                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                     20089                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                 612                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined           10307                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued               110                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved            283                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined         8241                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses              86                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency  4424.418605                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency  2424.418605                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency       380500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                86                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency       208500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           86                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               436                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency  4287.037037                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2287.037037                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     4                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency       1852000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.990826                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 432                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency       988000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.990826                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            432                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses             19                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency  4421.052632                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency  2421.052632                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency        84000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses               19                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency        46000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses           19                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.009685                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                522                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency  4309.845560                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency  2309.845560                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      4                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency        2232500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.992337                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  518                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency      1196500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.992337                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             518                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses               522                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency  4309.845560                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency  2309.845560                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     4                       # number of overall hits
system.cpu.l2cache.overall_miss_latency       2232500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.992337                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 518                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency      1196500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.992337                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            518                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   413                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               259.708792                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       4                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                            29982                       # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps           9868                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles             14192                       # Number of cycles rename is idle
system.cpu.rename.RENAME:RenameLookups          51924                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts           30001                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands        24487                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles               8874                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles            2909                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles            230                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps             14619                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles         3693                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts          648                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts               4472                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts          685                       # count of temporary serializing insts renamed
system.cpu.timesIdled                              20                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls

---------- End Simulation Statistics   ----------