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gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
sim_seconds 1.898652 # Number of seconds simulated
sim_ticks 1898652239500 # Number of ticks simulated
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
host_inst_rate 56630 # Simulator instruction rate (inst/s)
host_tick_rate 1915374267 # Simulator tick rate (ticks/s)
host_mem_usage 336120 # Number of bytes of host memory used
host_seconds 991.27 # Real time elapsed on the host
sim_insts 56136028 # Number of instructions simulated
system.l2c.replacements 398212 # number of replacements
system.l2c.tagsinuse 35264.339871 # Cycle average of tags in use
system.l2c.total_refs 2531779 # Total number of references to valid blocks.
system.l2c.sampled_refs 433064 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.846201 # Average number of references to valid blocks.
system.l2c.warmup_cycle 9253572000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0 10247.642027 # Average occupied blocks per context
system.l2c.occ_blocks::1 2471.458479 # Average occupied blocks per context
system.l2c.occ_blocks::2 22545.239365 # Average occupied blocks per context
system.l2c.occ_percent::0 0.156367 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.037711 # Average percentage of cache occupancy
system.l2c.occ_percent::2 0.344013 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0 988451 # number of ReadReq hits
system.l2c.ReadReq_hits::1 903729 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1892180 # number of ReadReq hits
system.l2c.Writeback_hits::0 854494 # number of Writeback hits
system.l2c.Writeback_hits::total 854494 # number of Writeback hits
system.l2c.UpgradeReq_hits::0 118 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1 98 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 216 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1 33 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0 107958 # number of ReadExReq hits
system.l2c.ReadExReq_hits::1 83389 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 191347 # number of ReadExReq hits
system.l2c.demand_hits::0 1096409 # number of demand (read+write) hits
system.l2c.demand_hits::1 987118 # number of demand (read+write) hits
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
system.l2c.demand_hits::total 2083527 # number of demand (read+write) hits
system.l2c.overall_hits::0 1096409 # number of overall hits
system.l2c.overall_hits::1 987118 # number of overall hits
system.l2c.overall_hits::2 0 # number of overall hits
system.l2c.overall_hits::total 2083527 # number of overall hits
system.l2c.ReadReq_misses::0 301714 # number of ReadReq misses
system.l2c.ReadReq_misses::1 8229 # number of ReadReq misses
system.l2c.ReadReq_misses::total 309943 # number of ReadReq misses
system.l2c.UpgradeReq_misses::0 2585 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3141 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0 58 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1 106 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 164 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0 104499 # number of ReadExReq misses
system.l2c.ReadExReq_misses::1 19805 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 124304 # number of ReadExReq misses
system.l2c.demand_misses::0 406213 # number of demand (read+write) misses
system.l2c.demand_misses::1 28034 # number of demand (read+write) misses
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
system.l2c.demand_misses::total 434247 # number of demand (read+write) misses
system.l2c.overall_misses::0 406213 # number of overall misses
system.l2c.overall_misses::1 28034 # number of overall misses
system.l2c.overall_misses::2 0 # number of overall misses
system.l2c.overall_misses::total 434247 # number of overall misses
system.l2c.ReadReq_miss_latency 16115869500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency 5950500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency 996000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency 6519390500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency 22635260000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency 22635260000 # number of overall miss cycles
system.l2c.ReadReq_accesses::0 1290165 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 911958 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2202123 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0 854494 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 854494 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0 2703 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1 654 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0 93 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1 139 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 232 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0 212457 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 103194 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 315651 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0 1502622 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 1015152 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2517774 # number of demand (read+write) accesses
system.l2c.overall_accesses::0 1502622 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 1015152 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2517774 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0 0.233857 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.009023 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0 0.956345 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1 0.850153 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0 0.623656 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1 0.762590 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0 0.491860 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 0.191920 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0 0.270336 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.027616 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
system.l2c.overall_miss_rate::0 0.270336 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.027616 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0 53414.390781 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 1958423.806052 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0 2301.934236 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 10702.338129 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0 17172.413793 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 9396.226415 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 62387.108968 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 329179.020449 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0 55722.638123 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 807421.702219 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_miss_latency::0 55722.638123 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 807421.702219 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks 122541 # number of writebacks
system.l2c.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits 22 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses 309921 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 3141 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses 164 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses 124304 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses 434225 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses 434225 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency 12396913500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency 125650000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency 6563500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency 5007569500 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency 17404483000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency 17404483000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 838548000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency 1423652498 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 2262200498 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.240218 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 0.339841 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0 1.162042 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 4.802752 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.763441 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.179856 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0 0.585078 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 1.204566 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0 0.288978 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 0.427744 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0 0.288978 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 0.427744 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40000.237157 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.183699 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40021.341463 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40284.862112 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41701 # number of replacements
system.iocache.tagsinuse 0.379408 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41717 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1709327692000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1 0.379408 # Average occupied blocks per context
system.iocache.occ_percent::1 0.023713 # Average percentage of cache occupancy
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.ReadReq_misses::1 179 # number of ReadReq misses
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 41731 # number of demand (read+write) misses
system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 41731 # number of overall misses
system.iocache.overall_misses::total 41731 # number of overall misses
system.iocache.ReadReq_miss_latency 20617998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency 5720950806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency 5741568804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency 5741568804 # number of overall miss cycles
system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115184.346369 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137681.719436 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137585.219717 # average overall miss latency
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137585.219717 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 64667028 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6183.498566 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks 41522 # number of writebacks
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency 11309998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency 3560091958 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency 3571401956 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 3571401956 # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 63184.346369 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85677.992828 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 6880123 # DTB read hits
system.cpu0.dtb.read_misses 27029 # DTB read misses
system.cpu0.dtb.read_acv 463 # DTB read access violations
system.cpu0.dtb.read_accesses 649764 # DTB read accesses
system.cpu0.dtb.write_hits 4434059 # DTB write hits
system.cpu0.dtb.write_misses 4980 # DTB write misses
system.cpu0.dtb.write_acv 206 # DTB write access violations
system.cpu0.dtb.write_accesses 207730 # DTB write accesses
system.cpu0.dtb.data_hits 11314182 # DTB hits
system.cpu0.dtb.data_misses 32009 # DTB misses
system.cpu0.dtb.data_acv 669 # DTB access violations
system.cpu0.dtb.data_accesses 857494 # DTB accesses
system.cpu0.itb.fetch_hits 880445 # ITB hits
system.cpu0.itb.fetch_misses 30276 # ITB misses
system.cpu0.itb.fetch_acv 796 # ITB acv
system.cpu0.itb.fetch_accesses 910721 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 86706401 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 9688854 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 8181343 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 315076 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 8774584 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 4716459 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.BPredUnit.usedRAS 623303 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 24682 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 18567041 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 50425492 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 9688854 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 5339762 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 9915303 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1544367 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 26514797 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 7883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 184619 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 223130 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6371925 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 198240 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 56424843 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.893675 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.198082 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 46509540 82.43% 82.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 722585 1.28% 83.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1421448 2.52% 86.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 628845 1.11% 87.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2255580 4.00% 91.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 483816 0.86% 92.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 510012 0.90% 93.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 672132 1.19% 94.29% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3220885 5.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 56424843 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.111743 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.581566 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 19801968 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 25882509 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8989466 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 763548 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 987351 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 383922 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 24849 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 49347154 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 75527 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 987351 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 20629203 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 9499998 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 13447452 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 8452255 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3408582 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 46738624 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 3619 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 624032 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1191344 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 31596053 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 57298293 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 57042075 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 256218 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 26711174 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4884879 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1120422 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 175328 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8812934 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 7283662 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 4733758 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1431112 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1440543 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 41212860 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1406639 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 39893176 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 57069 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5631702 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 3133217 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 960480 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 56424843 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.707014 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.300043 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 37805881 67.00% 67.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 8674612 15.37% 82.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4282035 7.59% 89.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2440705 4.33% 94.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1659937 2.94% 97.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 878759 1.56% 98.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 516481 0.92% 99.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 131514 0.23% 99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 34919 0.06% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 56424843 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 44960 12.13% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 2 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 207193 55.91% 68.04% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 118450 31.96% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 4482 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 27545306 69.05% 69.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 42376 0.11% 69.17% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 14767 0.04% 69.20% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 2231 0.01% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 7173118 17.98% 87.19% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 4487292 11.25% 98.44% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 623604 1.56% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 39893176 # Type of FU issued
system.cpu0.iq.rate 0.460095 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 370605 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.009290 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 136270898 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 48090698 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 38918381 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 367971 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 179542 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 176099 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 40067792 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 191507 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 416583 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1090641 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 12429 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 20965 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 441226 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 12240 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 165915 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 987351 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 6354184 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 491419 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 45032066 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 578341 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 7283662 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 4733758 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1245675 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 448555 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 7135 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 20965 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 225122 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 243860 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 468982 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 39459085 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 6924497 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 434091 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 2412567 # number of nop insts executed
system.cpu0.iew.exec_refs 11372805 # number of memory reference insts executed
system.cpu0.iew.exec_branches 6223343 # Number of branches executed
system.cpu0.iew.exec_stores 4448308 # Number of stores executed
system.cpu0.iew.exec_rate 0.455088 # Inst execution rate
system.cpu0.iew.wb_sent 39184807 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 39094480 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 19569580 # num instructions producing a value
system.cpu0.iew.wb_consumers 25865337 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.450883 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.756595 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts 38900399 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 6019570 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 446159 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 429799 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 55437492 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.701698 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.560671 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.commit.committed_per_cycle::0 40051862 72.25% 72.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6559971 11.83% 84.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3806221 6.87% 90.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1668838 3.01% 93.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1194660 2.15% 96.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 396856 0.72% 96.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 307618 0.55% 97.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 498884 0.90% 98.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 952582 1.72% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.commit.committed_per_cycle::total 55437492 # Number of insts commited each cycle
system.cpu0.commit.count 38900399 # Number of instructions committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.commit.refs 10485553 # Number of memory references committed
system.cpu0.commit.loads 6193021 # Number of loads committed
system.cpu0.commit.membars 147117 # Number of memory barriers committed
system.cpu0.commit.branches 5834794 # Number of branches committed
system.cpu0.commit.fp_insts 173443 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 36122415 # Number of committed integer instructions.
system.cpu0.commit.function_calls 477666 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 952582 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 99224913 # The number of ROB reads
system.cpu0.rob.rob_writes 90827622 # The number of ROB writes
system.cpu0.timesIdled 838575 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 30281558 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 36751342 # Number of Instructions Simulated
system.cpu0.committedInsts_total 36751342 # Number of Instructions Simulated
system.cpu0.cpi 2.359272 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.359272 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.423860 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.423860 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 52035955 # number of integer regfile reads
system.cpu0.int_regfile_writes 28508894 # number of integer regfile writes
system.cpu0.fp_regfile_reads 87486 # number of floating regfile reads
system.cpu0.fp_regfile_writes 87606 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1265189 # number of misc regfile reads
system.cpu0.misc_regfile_writes 638472 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 604064 # number of replacements
system.cpu0.icache.tagsinuse 509.990240 # Cycle average of tags in use
system.cpu0.icache.total_refs 5734171 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 604576 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 9.484616 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 23368350000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0 509.990240 # Average occupied blocks per context
system.cpu0.icache.occ_percent::0 0.996075 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0 5734171 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5734171 # number of ReadReq hits
system.cpu0.icache.demand_hits::0 5734171 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5734171 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0 5734171 # number of overall hits
system.cpu0.icache.overall_hits::1 0 # number of overall hits
system.cpu0.icache.overall_hits::total 5734171 # number of overall hits
system.cpu0.icache.ReadReq_misses::0 637754 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 637754 # number of ReadReq misses
system.cpu0.icache.demand_misses::0 637754 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 637754 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0 637754 # number of overall misses
system.cpu0.icache.overall_misses::1 0 # number of overall misses
system.cpu0.icache.overall_misses::total 637754 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency 9712599996 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency 9712599996 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency 9712599996 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0 6371925 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6371925 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0 6371925 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 6371925 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0 6371925 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 6371925 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0 0.100088 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0 0.100088 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0 0.100088 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 15229.383110 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 15229.383110 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 15229.383110 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1053998 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10435.623762 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks 253 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits 33035 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits 33035 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits 33035 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses 604719 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses 604719 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses 604719 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency 7372056498 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency 7372056498 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency 7372056498 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.094904 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0 0.094904 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0 0.094904 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12190.879562 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 899634 # number of replacements
system.cpu0.dcache.tagsinuse 446.158722 # Cycle average of tags in use
system.cpu0.dcache.total_refs 8155860 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 900023 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.061835 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0 447.158722 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0 0.873357 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0 5166195 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5166195 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0 2708345 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 2708345 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0 133652 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 133652 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0 151966 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 151966 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0 7874540 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 7874540 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0 7874540 # number of overall hits
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
system.cpu0.dcache.overall_hits::total 7874540 # number of overall hits
system.cpu0.dcache.ReadReq_misses::0 1064203 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1064203 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0 1419249 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1419249 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0 11793 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11793 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0 744 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 744 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0 2483452 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2483452 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0 2483452 # number of overall misses
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
system.cpu0.dcache.overall_misses::total 2483452 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency 27896641000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency 47260927840 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency 183691500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency 7368500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency 75157568840 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency 75157568840 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0 6230398 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6230398 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0 4127594 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4127594 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0 145445 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 145445 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0 152710 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 152710 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0 10357992 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 10357992 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0 10357992 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 10357992 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0 0.170808 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0 0.343844 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.081082 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0 0.004872 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0 0.239762 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0 0.239762 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 26213.646269 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.WriteReq_avg_miss_latency::0 33299.955004 # average WriteReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15576.316459 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9903.897849 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 30263.346680 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.overall_avg_miss_latency::0 30263.346680 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 831922069 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 188000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 93842 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8865.135749 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks 419465 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits 382209 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits 1203298 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits 2986 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits 1585507 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits 1585507 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses 681994 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses 215951 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses 8807 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses 744 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses 897945 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses 897945 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency 19802710500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency 7045833069 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 103680500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency 5132500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 5001 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency 26848543569 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency 26848543569 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634638000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1036991998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency 1671629998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109462 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.052319 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.060552 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.004872 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0 0.086691 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0 0.086691 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 29036.487858 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 32626.999037 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11772.510503 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6898.521505 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 4024884 # DTB read hits
system.cpu1.dtb.read_misses 17321 # DTB read misses
system.cpu1.dtb.read_acv 119 # DTB read access violations
system.cpu1.dtb.read_accesses 318700 # DTB read accesses
system.cpu1.dtb.write_hits 2545920 # DTB write hits
system.cpu1.dtb.write_misses 4459 # DTB write misses
system.cpu1.dtb.write_acv 131 # DTB write access violations
system.cpu1.dtb.write_accesses 133305 # DTB write accesses
system.cpu1.dtb.data_hits 6570804 # DTB hits
system.cpu1.dtb.data_misses 21780 # DTB misses
system.cpu1.dtb.data_acv 250 # DTB access violations
system.cpu1.dtb.data_accesses 452005 # DTB accesses
system.cpu1.itb.fetch_hits 565000 # ITB hits
system.cpu1.itb.fetch_misses 8360 # ITB misses
system.cpu1.itb.fetch_acv 355 # ITB acv
system.cpu1.itb.fetch_accesses 573360 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 36324508 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 5837794 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 4807752 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 236405 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 5114419 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 2355373 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.BPredUnit.usedRAS 425756 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 18870 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 12975380 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 28382917 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 5837794 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2781129 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 5303525 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 1029370 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 12998724 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 3277 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 80064 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 157005 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 3308770 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 142735 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 32191429 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.881692 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.232987 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 26887904 83.53% 83.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 353233 1.10% 84.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 711039 2.21% 86.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 413904 1.29% 88.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 842441 2.62% 90.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 260322 0.81% 91.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 338125 1.05% 92.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 409918 1.27% 93.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1974543 6.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 32191429 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.160712 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.781371 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 12951837 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 13394594 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 4901613 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 288063 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 655321 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 259847 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 18216 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 27639459 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 54136 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 655321 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 13441589 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 3341745 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 8668513 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 4556322 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1527937 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 25800670 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 384 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 324513 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 337358 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 16998396 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 30868000 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 30637033 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 230967 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 13782341 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 3216047 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 763704 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 85939 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 4786247 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 4278315 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 2704053 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 527948 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 347634 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 22339353 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 928348 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 21581640 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 44138 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 3694956 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 1842331 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 660792 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 32191429 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.670416 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.349411 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 23032002 71.55% 71.55% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 3880534 12.05% 83.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1841751 5.72% 89.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1343655 4.17% 93.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 1100926 3.42% 96.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 572017 1.78% 98.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 269219 0.84% 99.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 103064 0.32% 99.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 48261 0.15% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 32191429 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 27325 8.19% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 173483 52.02% 60.21% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 132688 39.79% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 2823 0.01% 0.01% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 14285140 66.19% 66.20% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 29916 0.14% 66.34% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.34% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 11006 0.05% 66.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 4218514 19.55% 85.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 2587729 11.99% 97.94% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 445101 2.06% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 21581640 # Type of FU issued
system.cpu1.iq.rate 0.594134 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 333496 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.015453 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 75401338 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 26810016 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 20892220 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 331004 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 159326 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 156915 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 21738437 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 173876 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 181996 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 722762 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 9242 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 8212 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 265030 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 7445 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 45661 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 655321 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 2533054 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 130038 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 24654122 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 348083 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 4278315 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 2704053 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 831283 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 42195 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 6811 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 8212 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 170867 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 176891 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 347758 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 21288201 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 4056224 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 293438 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 1386421 # number of nop insts executed
system.cpu1.iew.exec_refs 6615012 # number of memory reference insts executed
system.cpu1.iew.exec_branches 3371082 # Number of branches executed
system.cpu1.iew.exec_stores 2558788 # Number of stores executed
system.cpu1.iew.exec_rate 0.586056 # Inst execution rate
system.cpu1.iew.wb_sent 21107487 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 21049135 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 10120752 # num instructions producing a value
system.cpu1.iew.wb_consumers 14228146 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.579475 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.711319 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 20574037 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 4003646 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 267556 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 316871 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 31536108 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.652396 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.582786 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.commit.committed_per_cycle::0 23929669 75.88% 75.88% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 3216209 10.20% 86.08% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1611477 5.11% 91.19% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 871112 2.76% 93.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 572339 1.81% 95.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 274054 0.87% 96.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 208667 0.66% 97.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 210738 0.67% 97.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 641843 2.04% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.commit.committed_per_cycle::total 31536108 # Number of insts commited each cycle
system.cpu1.commit.count 20574037 # Number of instructions committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.commit.refs 5994576 # Number of memory references committed
system.cpu1.commit.loads 3555553 # Number of loads committed
system.cpu1.commit.membars 91088 # Number of memory barriers committed
system.cpu1.commit.branches 3081632 # Number of branches committed
system.cpu1.commit.fp_insts 155618 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 18958031 # Number of committed integer instructions.
system.cpu1.commit.function_calls 316244 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 641843 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 55370614 # The number of ROB reads
system.cpu1.rob.rob_writes 49810796 # The number of ROB writes
system.cpu1.timesIdled 461933 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 4133079 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.committedInsts 19384686 # Number of Instructions Simulated
system.cpu1.committedInsts_total 19384686 # Number of Instructions Simulated
system.cpu1.cpi 1.873877 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.873877 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.533653 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.533653 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 27536671 # number of integer regfile reads
system.cpu1.int_regfile_writes 15012037 # number of integer regfile writes
system.cpu1.fp_regfile_reads 81305 # number of floating regfile reads
system.cpu1.fp_regfile_writes 82180 # number of floating regfile writes
system.cpu1.misc_regfile_reads 884105 # number of misc regfile reads
system.cpu1.misc_regfile_writes 384773 # number of misc regfile writes
system.cpu1.icache.replacements 474445 # number of replacements
system.cpu1.icache.tagsinuse 505.356684 # Cycle average of tags in use
system.cpu1.icache.total_refs 2809266 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 474955 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 5.914805 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 46541421000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0 505.356684 # Average occupied blocks per context
system.cpu1.icache.occ_percent::0 0.987025 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0 2809266 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 2809266 # number of ReadReq hits
system.cpu1.icache.demand_hits::0 2809266 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 2809266 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0 2809266 # number of overall hits
system.cpu1.icache.overall_hits::1 0 # number of overall hits
system.cpu1.icache.overall_hits::total 2809266 # number of overall hits
system.cpu1.icache.ReadReq_misses::0 499504 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 499504 # number of ReadReq misses
system.cpu1.icache.demand_misses::0 499504 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 499504 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0 499504 # number of overall misses
system.cpu1.icache.overall_misses::1 0 # number of overall misses
system.cpu1.icache.overall_misses::total 499504 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency 7358434998 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency 7358434998 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency 7358434998 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0 3308770 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 3308770 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0 3308770 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 3308770 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0 3308770 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 3308770 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0 0.150964 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0 0.150964 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0 0.150964 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 14731.483628 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 14731.483628 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 14731.483628 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 428499 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 44 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 9738.613636 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks 33 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits 24498 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits 24498 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits 24498 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses 475006 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses 475006 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses 475006 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency 5595943999 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency 5595943999 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency 5595943999 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143560 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0 0.143560 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0 0.143560 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11780.785925 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 557180 # number of replacements
system.cpu1.dcache.tagsinuse 488.553100 # Cycle average of tags in use
system.cpu1.dcache.total_refs 4834021 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 557692 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 8.667905 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 34444090000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0 488.553100 # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0 0.954205 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0 2945256 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2945256 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0 1749855 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1749855 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0 63493 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 63493 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0 71374 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 71374 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0 4695111 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 4695111 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0 4695111 # number of overall hits
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
system.cpu1.dcache.overall_hits::total 4695111 # number of overall hits
system.cpu1.dcache.ReadReq_misses::0 787154 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 787154 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0 609216 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 609216 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0 13718 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 13718 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0 830 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 830 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0 1396370 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 1396370 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0 1396370 # number of overall misses
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
system.cpu1.dcache.overall_misses::total 1396370 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency 11151181000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency 13606670637 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency 199877000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency 10316000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency 24757851637 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency 24757851637 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0 3732410 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3732410 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0 2359071 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 2359071 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0 77211 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 77211 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0 72204 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 72204 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0 6091481 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 6091481 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0 6091481 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 6091481 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0 0.210897 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0 0.258244 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.177669 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0 0.011495 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0 0.229233 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0 0.229233 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 14166.454086 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.WriteReq_avg_miss_latency::0 22334.723049 # average WriteReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14570.418428 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12428.915663 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 17730.151491 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.overall_avg_miss_latency::0 17730.151491 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 143111212 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 13232 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10815.538996 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks 434743 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits 338033 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits 504690 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits 2893 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits 842723 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits 842723 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses 449121 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses 104526 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses 10825 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses 830 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses 553647 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses 553647 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency 5367032500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency 2133420198 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 121712000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency 7814500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency 7500452698 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency 7500452698 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 301848000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 539476500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency 841324500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120330 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.044308 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140200 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.011495 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0 0.090889 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0 0.090889 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11950.081381 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20410.426095 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11243.602771 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9415.060241 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 139328 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 46150 38.89% 38.89% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 238 0.20% 39.09% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1923 1.62% 40.71% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 16 0.01% 40.73% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 70336 59.27% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 118663 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 45525 48.84% 48.84% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 238 0.26% 49.10% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1923 2.06% 51.16% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 45509 48.82% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 93211 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1865602561500 98.27% 98.27% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 91021500 0.00% 98.28% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 389859500 0.02% 98.30% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 7895500 0.00% 98.30% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 32350102500 1.70% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1898441440500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.986457 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.647023 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 5 2.39% 2.39% # number of syscalls executed
system.cpu0.kern.syscall::3 17 8.13% 10.53% # number of syscalls executed
system.cpu0.kern.syscall::4 3 1.44% 11.96% # number of syscalls executed
system.cpu0.kern.syscall::6 28 13.40% 25.36% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.48% 25.84% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.48% 26.32% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.31% 30.62% # number of syscalls executed
system.cpu0.kern.syscall::19 5 2.39% 33.01% # number of syscalls executed
system.cpu0.kern.syscall::20 4 1.91% 34.93% # number of syscalls executed
system.cpu0.kern.syscall::23 2 0.96% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::24 4 1.91% 37.80% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.35% 41.15% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.96% 42.11% # number of syscalls executed
system.cpu0.kern.syscall::45 35 16.75% 58.85% # number of syscalls executed
system.cpu0.kern.syscall::47 4 1.91% 60.77% # number of syscalls executed
system.cpu0.kern.syscall::48 6 2.87% 63.64% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.31% 67.94% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.48% 68.42% # number of syscalls executed
system.cpu0.kern.syscall::59 4 1.91% 70.33% # number of syscalls executed
system.cpu0.kern.syscall::71 32 15.31% 85.65% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.44% 87.08% # number of syscalls executed
system.cpu0.kern.syscall::74 9 4.31% 91.39% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed
system.cpu0.kern.syscall::90 1 0.48% 92.34% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.35% 95.69% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed
system.cpu0.kern.syscall::132 2 0.96% 98.56% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 209 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 105 0.08% 0.08% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed
system.cpu0.kern.callpal::swpctx 2219 1.77% 1.85% # number of callpals executed
system.cpu0.kern.callpal::tbi 37 0.03% 1.88% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.01% 1.89% # number of callpals executed
system.cpu0.kern.callpal::swpipl 112588 89.60% 91.49% # number of callpals executed
system.cpu0.kern.callpal::rdps 6309 5.02% 96.51% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.51% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.52% # number of callpals executed
system.cpu0.kern.callpal::rdusp 6 0.00% 96.52% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.52% # number of callpals executed
system.cpu0.kern.callpal::rti 3897 3.10% 99.62% # number of callpals executed
system.cpu0.kern.callpal::callsys 326 0.26% 99.88% # number of callpals executed
system.cpu0.kern.callpal::imb 146 0.12% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 125650 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5507 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1097
system.cpu0.kern.mode_good::user 1097
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.199201 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1896108272000 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1865257500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 2220 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.inst.quiesce 3828 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 98562 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 35646 40.41% 40.41% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1921 2.18% 42.59% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 105 0.12% 42.71% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 50532 57.29% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 88204 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 34894 48.66% 48.66% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1921 2.68% 51.34% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 105 0.15% 51.49% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 34789 48.51% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 71709 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1866332283500 98.30% 98.30% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 346173000 0.02% 98.32% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 42378500 0.00% 98.32% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 31930549500 1.68% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1898651384500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.978904 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.ipl_used::31 0.688455 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 3 2.56% 2.56% # number of syscalls executed
system.cpu1.kern.syscall::3 13 11.11% 13.68% # number of syscalls executed
system.cpu1.kern.syscall::4 1 0.85% 14.53% # number of syscalls executed
system.cpu1.kern.syscall::6 14 11.97% 26.50% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.13% 31.62% # number of syscalls executed
system.cpu1.kern.syscall::19 5 4.27% 35.90% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.71% 37.61% # number of syscalls executed
system.cpu1.kern.syscall::23 2 1.71% 39.32% # number of syscalls executed
system.cpu1.kern.syscall::24 2 1.71% 41.03% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.42% 44.44% # number of syscalls executed
system.cpu1.kern.syscall::45 19 16.24% 60.68% # number of syscalls executed
system.cpu1.kern.syscall::47 2 1.71% 62.39% # number of syscalls executed
system.cpu1.kern.syscall::48 4 3.42% 65.81% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.85% 66.67% # number of syscalls executed
system.cpu1.kern.syscall::59 3 2.56% 69.23% # number of syscalls executed
system.cpu1.kern.syscall::71 22 18.80% 88.03% # number of syscalls executed
system.cpu1.kern.syscall::74 7 5.98% 94.02% # number of syscalls executed
system.cpu1.kern.syscall::90 2 1.71% 95.73% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.71% 97.44% # number of syscalls executed
system.cpu1.kern.syscall::132 2 1.71% 99.15% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 117 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::swpctx 2023 2.23% 2.25% # number of callpals executed
system.cpu1.kern.callpal::tbi 16 0.02% 2.26% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.27% # number of callpals executed
system.cpu1.kern.callpal::swpipl 82767 91.03% 93.30% # number of callpals executed
system.cpu1.kern.callpal::rdps 2444 2.69% 95.99% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 95.99% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.00% 96.00% # number of callpals executed
system.cpu1.kern.callpal::rdusp 3 0.00% 96.00% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 96.00% # number of callpals executed
system.cpu1.kern.callpal::rti 3410 3.75% 99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys 189 0.21% 99.96% # number of callpals executed
system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 90921 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2651 # number of protection mode switches
system.cpu1.kern.mode_switch::user 640 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2049 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 706
system.cpu1.kern.mode_good::user 640
system.cpu1.kern.mode_good::idle 66
system.cpu1.kern.mode_switch_good::kernel 0.266315 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.mode_switch_good::idle 0.032211 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 1.298525 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 43748791000 2.30% 2.30% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 905692500 0.05% 2.35% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1853996893000 97.65% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2024 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
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