2008-10-21 01:00:07 +02:00
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---------- Begin Simulation Statistics ----------
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2011-01-18 23:30:06 +01:00
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host_inst_rate 145689 # Simulator instruction rate (inst/s)
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host_mem_usage 291364 # Number of bytes of host memory used
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host_seconds 364.14 # Real time elapsed on the host
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host_tick_rate 5126322811 # Simulator tick rate (ticks/s)
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2008-10-21 01:00:07 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-01-18 23:30:06 +01:00
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sim_insts 53051251 # Number of instructions simulated
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sim_seconds 1.866703 # Number of seconds simulated
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sim_ticks 1866702838500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBHits 6623157 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 12789444 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 40569 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 601028 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 11937575 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 14339384 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1014923 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 8457250 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 1007675 # number cycles where commit BW limit reached
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2008-10-21 01:00:07 +02:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::samples 89231545 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.630319 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.393269 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::0 65110491 72.97% 72.97% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 10643752 11.93% 84.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 6057329 6.79% 91.68% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 2842358 3.19% 94.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 2098441 2.35% 97.22% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 701144 0.79% 98.01% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 394504 0.44% 98.45% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 375851 0.42% 98.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 1007675 1.13% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle
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system.cpu.commit.COM:count 56244349 # Number of instructions committed
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system.cpu.commit.COM:loads 9107235 # Number of loads committed
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system.cpu.commit.COM:membars 227951 # Number of memory barriers committed
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system.cpu.commit.COM:refs 15496318 # Number of memory references committed
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2008-10-21 01:00:07 +02:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.branchMispredicts 771510 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 56244349 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 667563 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8699299 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 53051251 # Number of Instructions Simulated
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system.cpu.committedInsts_total 53051251 # Number of Instructions Simulated
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system.cpu.cpi 2.358137 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.358137 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses::0 215722 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 215722 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14725.540425 # average LoadLockedReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.875143 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits::0 193471 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 193471 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 327658000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103147 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 22251 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 22251 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 4791 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207475000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080938 # mshr miss rate for LoadLockedReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_misses 17460 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses::0 9297964 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 9297964 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.133732 # average ReadReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.439279 # average ReadReq mshr miss latency
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2008-10-21 01:00:07 +02:00
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.ReadReq_hits::0 7723736 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7723736 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 35761948000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.169309 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 1574228 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1574228 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 490302 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 24691226500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116577 # mshr miss rate for ReadReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.ReadReq_mshr_misses 1083926 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905134500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 219685 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 219685 # number of StoreCondReq accesses(hits+misses)
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.StoreCondReq_hits::0 219682 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 219682 # number of StoreCondReq hits
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 33000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 # mshr miss rate for StoreCondReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_accesses::0 6154252 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6154252 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 29747.302403 # average WriteReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28091.080381 # average WriteReq mshr miss latency
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2008-10-21 01:00:07 +02:00
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_hits::0 4299090 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4299090 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 55186065021 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.301444 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 1855162 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 1855162 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1555538 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 8416761868 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048686 # mshr miss rate for WriteReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.WriteReq_mshr_misses 299624 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235207998 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 8963.151072 # average number of cycles each access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.avg_refs 8.877326 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 83371 # number of cycles access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked_cycles::no_mshrs 747266868 # number of cycles access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2008-10-21 01:00:07 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_accesses::0 15452216 # number of demand (read+write) accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_accesses::total 15452216 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 26520.172107 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 12022826 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_hits::total 12022826 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 90948013021 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.221935 # miss rate for demand accesses
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_misses::0 3429390 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
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|
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
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|
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system.cpu.dcache.demand_misses::total 3429390 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2045840 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 33107988368 # number of demand (read+write) MSHR miss cycles
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|
|
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system.cpu.dcache.demand_mshr_miss_rate::0 0.089537 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
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|
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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|
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
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system.cpu.dcache.demand_mshr_misses 1383550 # number of demand (read+write) MSHR misses
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2008-10-21 01:00:07 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-02-25 19:08:41 +01:00
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system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
|
2011-01-18 23:30:06 +01:00
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system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 15452216 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
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|
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
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|
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system.cpu.dcache.overall_accesses::total 15452216 # number of overall (read+write) accesses
|
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|
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system.cpu.dcache.overall_avg_miss_latency::0 26520.172107 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
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|
|
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_hits::0 12022826 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_hits::total 12022826 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 90948013021 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::0 0.221935 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_misses::0 3429390 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_misses::total 3429390 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2045840 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 33107988368 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.089537 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_mshr_misses 1383550 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 2140342498 # number of overall MSHR uncacheable cycles
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.replacements 1400366 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 1400878 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 12436050 # Total number of references to valid blocks.
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.writebacks 832764 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 37803166 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 42143 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 613837 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 71397647 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 37493968 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 12849862 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 1515496 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 134350 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 1084548 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.dtb.data_accesses 1235511 # DTB accesses
|
|
|
|
|
system.cpu.dtb.data_acv 814 # DTB access violations
|
|
|
|
|
system.cpu.dtb.data_hits 16593720 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 46888 # DTB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dtb.read_accesses 910670 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_acv 580 # DTB read access violations
|
|
|
|
|
system.cpu.dtb.read_hits 10006545 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 38646 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 324841 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_acv 234 # DTB write access violations
|
|
|
|
|
system.cpu.dtb.write_hits 6587175 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 8242 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 14339384 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 8856318 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 14115387 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 454337 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 72663163 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 43087 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.SquashCycles 884394 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.114621 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 8856315 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 7638080 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.580831 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 90747041 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.800722 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::0 76631654 84.45% 84.45% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 1046048 1.15% 85.60% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1970042 2.17% 87.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 921005 1.01% 88.78% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 2984540 3.29% 92.07% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 648959 0.72% 92.79% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 776516 0.86% 93.64% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 1074251 1.18% 94.83% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 4694026 5.17% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.426022 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits::0 7816051 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 7816051 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 15556494000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.117460 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::0 1040267 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1040267 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 47648 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 11850308500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112080 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 992619 # number of ReadReq MSHR misses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.avg_refs 7.875653 # Average number of references to valid blocks.
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_accesses::0 8856318 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_accesses::total 8856318 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 14954.328072 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits::0 7816051 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_hits::total 7816051 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 15556494000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.117460 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_misses::0 1040267 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_misses::total 1040267 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 47648 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 11850308500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.112080 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 992619 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 509.811601 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses::0 8856318 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_accesses::total 8856318 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 14954.328072 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_hits::0 7816051 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_hits::total 7816051 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 15556494000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate::0 0.117460 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_misses::0 1040267 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_misses::total 1040267 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 47648 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 11850308500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.112080 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 992619 # number of overall MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.replacements 991921 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 992432 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.tagsinuse 509.811601 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 7816050 # Total number of references to valid blocks.
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit.
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.writebacks 92 # number of writebacks
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.idleCycles 34355081 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 9120774 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 3587033 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.456767 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 16683612 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 6610329 # Number of stores executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.WB:consumers 35257849 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 56697227 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.757274 # average fanout of values written-back
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.WB:producers 26699852 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.453208 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 56799146 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 837773 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 9250897 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 10628246 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1790214 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 887997 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 6943382 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 65075490 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 10073283 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 520965 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 57142461 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 61275 # Number of times the IQ has become full, causing a stall
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewLSQFullEvents 11738 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 1515496 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 557834 # Number of cycles IEW is unblocking
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 132328 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 438613 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 9607 # Number of memory responses ignored because the instruction is squashed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 42661 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 17611 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1521011 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 554299 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 39527901 68.55% 68.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 62346 0.11% 68.67% # Type of FU issued
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 10424527 18.08% 86.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659257 11.55% 98.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 952873 1.65% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 57663428 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 432905 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007507 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 49058 11.33% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.33% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 267419 61.77% 73.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 116428 26.89% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 90747041 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635430 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200309 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 62366198 68.73% 68.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 14061379 15.50% 84.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 6226874 6.86% 91.08% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 3821617 4.21% 95.29% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 2539194 2.80% 98.09% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 1091409 1.20% 99.29% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 462366 0.51% 99.80% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 128599 0.14% 99.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 49405 0.05% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 8060465 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 28817 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1372188 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 4168617 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.itb.fetch_accesses 1294583 # ITB accesses
|
|
|
|
|
system.cpu.itb.fetch_acv 923 # ITB acv
|
|
|
|
|
system.cpu.itb.fetch_hits 1255493 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 39090 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.callpal::swpipl 175591 91.19% 93.39% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.callpal::total 192561 # number of callpals executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.inst.hwrei 211718 # number of hwrei instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 6427 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.kern.ipl_count::0 74916 40.95% 40.95% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::21 238 0.13% 41.08% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::31 105896 57.89% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::total 182940 # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_good::0 73549 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::21 238 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::31 73550 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::total 149227 # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::0 1827171336500 97.88% 97.88% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::21 97547000 0.01% 97.89% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::22 392033000 0.02% 97.91% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::31 39041048500 2.09% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::total 1866701965000 # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.ipl_used::31 0.694549 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.mode_good::kernel 1906
|
|
|
|
|
system.cpu.kern.mode_good::user 1736
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.mode_good::idle 170
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch::user 1736 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch::idle 2107 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.kern.mode_switch_good::idle 0.080683 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_good::total 1.400697 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu.kern.mode_ticks::kernel 30086574000 1.61% 1.61% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks::user 3015068000 0.16% 1.77% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks::idle 1833600315000 98.23% 100.00% # number of ticks spent at the given mode
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 3018201 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 125102122 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 39060011 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 1661101 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 58596 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 82213921 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 67573183 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 45293711 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 12514369 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2008-10-21 01:00:07 +02:00
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
2010-12-08 01:19:57 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2010-12-08 01:19:57 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_avg_miss_latency::1 137707.205574 # average WriteReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85703.600260 # average WriteReq mshr miss latency
|
|
|
|
|
system.iocache.WriteReq_miss_latency 5722009806 # number of WriteReq miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
|
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_latency 3561155998 # number of WriteReq MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6170.205040 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2010-09-22 08:07:35 +02:00
|
|
|
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 64639068 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_avg_miss_latency::1 137614.087573 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_miss_latency 5741947804 # number of demand (read+write) miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_mshr_miss_latency 3572097996 # number of demand (read+write) MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.occ_%::1 0.081528 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.occ_blocks::1 1.304443 # Average occupied blocks per context
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_avg_miss_latency::1 137614.087573 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_miss_latency 5741947804 # number of overall miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 41725 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_mshr_miss_latency 3572097996 # number of overall MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.replacements 41685 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.tagsinuse 1.304443 # Cycle average of tags in use
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.warmup_cycle 1711281262000 # Cycle when the warmup percentage was hit.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.writebacks 41512 # number of writebacks
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_accesses::0 300850 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 300850 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52488.966283 # average ReadExReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40339.814538 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_hits::0 183845 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 183845 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 6141471500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 0.388915 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 117005 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 117005 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 4719960000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.388915 # mshr miss rate for ReadExReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_mshr_misses 117005 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 2092533 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 2092533 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 52046.060634 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40015.025123 # average ReadReq mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_hits::0 1785047 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1785047 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 16003435000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.146944 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 307486 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 307486 # number of ReadReq misses
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency 12304020000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.146944 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_mshr_misses 307485 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 810593000 # number of ReadReq MSHR uncacheable cycles
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_accesses::0 25 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 21400 # average UpgradeReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 44000 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_hits::0 10 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 10 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 321000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.600000 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 15 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 15 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 660000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.600000 # mshr miss rate for UpgradeReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1115666998 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses::0 832856 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 832856 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 832856 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 832856 # number of Writeback hits
|
2009-04-22 19:25:17 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.avg_refs 5.629154 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_accesses::0 2393383 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_accesses::total 2393383 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 52168.141374 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits::0 1968892 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_hits::total 1968892 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 22144906500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.177360 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_misses::0 424491 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_misses::total 424491 # number of demand (read+write) misses
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_mshr_miss_latency 17023980000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.177360 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_mshr_misses 424490 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.occ_%::0 0.186942 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::1 0.344679 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_blocks::0 12251.423039 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 22588.894949 # Average occupied blocks per context
|
|
|
|
|
system.l2c.overall_accesses::0 2393383 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_accesses::total 2393383 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 52168.141374 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_hits::0 1968892 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_hits::total 1968892 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 22144906500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.177360 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_misses::0 424491 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_misses::total 424491 # number of overall misses
|
2010-11-08 20:58:24 +01:00
|
|
|
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_mshr_miss_latency 17023980000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.177360 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_mshr_misses 424490 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 1926259998 # number of overall MSHR uncacheable cycles
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.replacements 390992 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 423734 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.tagsinuse 34840.317988 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 2385264 # Total number of references to valid blocks.
|
2010-09-22 08:07:35 +02:00
|
|
|
system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.writebacks 117628 # number of writebacks
|
2009-04-22 19:25:17 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
2008-10-21 01:00:07 +02:00
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
