gem5/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 463084                       # Simulator instruction rate (inst/s)
host_mem_usage                                 236284                       # Number of bytes of host memory used
host_seconds                                   293.98                       # Real time elapsed on the host
host_tick_rate                              690315679                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   136139203                       # Number of instructions simulated
sim_seconds                                  0.202942                       # Number of seconds simulated
sim_ticks                                202941992000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               37185802                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     1709246000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                45499                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency   1572749000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses           45499                       # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency        30800                       # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency        27800                       # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency         462000                       # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency       417000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              20759140                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency    5738404000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.005040                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              105164                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency   5422912000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.005040                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         105164                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 49432.508313                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency      7447650000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency   6995661000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.997953                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               57944942                       # number of overall hits
system.cpu.dcache.overall_miss_latency     7447650000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               150663                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency   6995661000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 146582                       # number of replacements
system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4087.617150                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   118818                       # number of writebacks
system.cpu.icache.ReadReq_accesses          134553584                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 16930.864488                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              134366560                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency     3166478000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.001390                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency   2605406000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.001390                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           134553584                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 16930.864488                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
system.cpu.icache.demand_hits               134366560                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency      3166478000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.001390                       # miss rate for demand accesses
system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency   2605406000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.001390                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.978868                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              134366560                       # number of overall hits
system.cpu.icache.overall_miss_latency     3166478000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.001390                       # miss rate for overall accesses
system.cpu.icache.overall_misses               187024                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency   2605406000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.001390                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                 184976                       # number of replacements
system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               2004.721102                       # Cycle average of tags in use
system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle           144544557000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses          105179                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits                3599                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   5282160000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.965782                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            101580                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   4063200000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.965782                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       101580                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            232523                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                193942                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    2006212000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.165923                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               38581                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1543240000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165923                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          38581                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses          118818                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              118818                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  1.525179                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             337702                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 197541                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     7288372000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.415043                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               140161                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   5606440000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.415043                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          140161                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.121030                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.481204                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                197541                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    7288372000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.415043                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              140161                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   5606440000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.415043                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         140161                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                120138                       # number of replacements
system.cpu.l2cache.sampled_refs                139002                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             19734.031622                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  212003                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   87265                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.num_busy_cycles                  405883984                       # Number of busy cycles
system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
system.cpu.num_fp_insts                       2326977                       # number of float instructions
system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_insts                        136139203                       # Number of instructions executed
system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
system.cpu.num_int_insts                    115187758                       # number of integer instructions
system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
system.cpu.num_int_register_writes          113225732                       # number of times the integer registers were written
system.cpu.num_load_insts                    37275868                       # Number of load instructions
system.cpu.num_mem_refs                      58160249                       # number of memory refs
system.cpu.num_store_insts                   20884381                       # Number of store instructions
system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls

---------- End Simulation Statistics   ----------