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gem5/util/m5/m5op_arm.S

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ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Ali Saidi
* Chander Sudanthi
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
* Andreas Sandberg
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
*/
ARM: Update m5op assembly for thumb compilation.
2012-05-11 01:04:26 +02:00
.syntax unified
#ifdef __thumb__
.thumb
#endif
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
#include "m5ops.h"
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
.text
.macro simple_op name, func, subfunc
arm: Fix compilation error in m5 utility Changeset 5ca6098b9560 accidentally broke the m5 utility. This changeset adds the missing co-processor call used to trigger the pseudo-op in ARM mode and fixes an alignment issue that caused some pseudo-ops to leave thumb mode.
2013-05-14 15:03:45 +02:00
.align 2
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
.globl \name
\name:
ARM: Update m5op assembly for thumb compilation.
2012-05-11 01:04:26 +02:00
#ifdef __thumb__
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
.short 0xEE00 | \func
.short 0x0110 | (\subfunc << 12)
ARM: Update m5op assembly for thumb compilation.
2012-05-11 01:04:26 +02:00
#else
arm: fix m5ops binary for ARM and add m5fail. Changes to make m5ops work under virtualization seemed to break them working with non-virtualized systems and the recently added m5 fail command makes the m5op binary not compile. For now remove the code for virtualization.
2013-10-31 19:41:13 +01:00
.long 0xEE000110 | (\func << 16) | (\subfunc << 12)
ARM: Update m5op assembly for thumb compilation.
2012-05-11 01:04:26 +02:00
#endif
arm: fix m5ops binary for ARM and add m5fail. Changes to make m5ops work under virtualization seemed to break them working with non-virtualized systems and the recently added m5 fail command makes the m5op binary not compile. For now remove the code for virtualization.
2013-10-31 19:41:13 +01:00
mov pc,lr
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
.endm
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
#define SIMPLE_OP(name, func, subfunc) simple_op name, func, subfunc
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
SIMPLE_OP(arm, arm_func, 0)
SIMPLE_OP(quiesce, quiesce_func, 0)
SIMPLE_OP(quiesceNs, quiescens_func, 0)
SIMPLE_OP(quiesceCycle, quiescecycle_func, 0)
SIMPLE_OP(quiesceTime, quiescetime_func, 0)
SIMPLE_OP(rpns, rpns_func, 0)
SIMPLE_OP(wakeCPU, wakecpu_func, 0)
SIMPLE_OP(m5_exit, exit_func, 0)
arm: Add support for the m5fail pseudo-op
2013-05-14 15:06:50 +02:00
SIMPLE_OP(m5_fail, fail_func, 0)
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
SIMPLE_OP(m5_initparam, initparam_func, 0)
SIMPLE_OP(m5_loadsymbol, loadsymbol_func, 0)
SIMPLE_OP(m5_reset_stats, resetstats_func, 0)
SIMPLE_OP(m5_dump_stats, dumpstats_func, 0)
SIMPLE_OP(m5_dumpreset_stats, dumprststats_func, 0)
SIMPLE_OP(m5_checkpoint, ckpt_func, 0)
SIMPLE_OP(m5_readfile, readfile_func, 0)
SIMPLE_OP(m5_writefile, writefile_func, 0)
SIMPLE_OP(m5_debugbreak, debugbreak_func, 0)
SIMPLE_OP(m5_switchcpu, switchcpu_func, 0)
SIMPLE_OP(m5_addsymbol, addsymbol_func, 0)
SIMPLE_OP(m5_panic, panic_func, 0)
SIMPLE_OP(m5_work_begin, work_begin_func, 0)
SIMPLE_OP(m5_work_end, work_end_func, 0)
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 20:58:24 +01:00
kvm: Add support for pseudo-ops on ARM This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-04-22 19:20:32 +02:00
SIMPLE_OP(m5a_bsm, annotate_func, an_bsm)
SIMPLE_OP(m5a_esm, annotate_func, an_esm)
SIMPLE_OP(m5a_begin, annotate_func, an_begin)
SIMPLE_OP(m5a_end, annotate_func, an_end)
SIMPLE_OP(m5a_q, annotate_func, an_q)
SIMPLE_OP(m5a_rq, annotate_func, an_rq)
SIMPLE_OP(m5a_dq, annotate_func, an_dq)
SIMPLE_OP(m5a_wf, annotate_func, an_wf)
SIMPLE_OP(m5a_we, annotate_func, an_we)
SIMPLE_OP(m5a_ws, annotate_func, an_ws)
SIMPLE_OP(m5a_sq, annotate_func, an_sq)
SIMPLE_OP(m5a_aq, annotate_func, an_aq)
SIMPLE_OP(m5a_pq, annotate_func, an_pq)
SIMPLE_OP(m5a_l, annotate_func, an_l)
SIMPLE_OP(m5a_identify, annotate_func, an_identify)
SIMPLE_OP(m5a_getid, annotate_func, an_getid)
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