119 lines
4.6 KiB
C
119 lines
4.6 KiB
C
// See MultiProcessor Specification Version 1.[14].
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struct mp { // floating pointer
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uchar signature[4]; // "_MP_"
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void *physaddr; // phys addr of MP config table
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uchar length; // 1
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uchar specrev; // [14]
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uchar checksum; // all bytes must add up to 0
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uchar type; // MP system config type
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uchar imcrp;
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uchar reserved[3];
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};
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struct mpctb { // configuration table header
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uchar signature[4]; // "PCMP"
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ushort length; // total table length
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uchar version; // [14]
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uchar checksum; // all bytes must add up to 0
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uchar product[20]; // product id
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uint *oemtable; // OEM table pointer
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ushort oemlength; // OEM table length
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ushort entry; // entry count
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uint *lapicaddr; // address of local APIC
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ushort xlength; // extended table length
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uchar xchecksum; // extended table checksum
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uchar reserved;
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};
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struct mppe { // processor table entry
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uchar type; // entry type (0)
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uchar apicid; // local APIC id
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uchar version; // local APIC verison
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uchar flags; // CPU flags
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uchar signature[4]; // CPU signature
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uint feature; // feature flags from CPUID instruction
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uchar reserved[8];
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};
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struct mpbe { // bus table entry
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uchar type; // entry type (1)
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uchar busno; // bus id
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char string[6]; // bus type string
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};
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struct mpioapic { // I/O APIC table entry
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uchar type; // entry type (2)
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uchar apicno; // I/O APIC id
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uchar version; // I/O APIC version
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uchar flags; // I/O APIC flags
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uint *addr; // I/O APIC address
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};
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struct mpie { // interrupt table entry
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uchar type; // entry type ([34])
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uchar intr; // interrupt type
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ushort flags; // interrupt flag
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uchar busno; // source bus id
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uchar irq; // source bus irq
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uchar apicno; // destination APIC id
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uchar intin; // destination APIC [L]INTIN#
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};
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enum { // table entry types
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MPPROCESSOR = 0x00, // one entry per processor
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MPBUS = 0x01, // one entry per bus
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MPIOAPIC = 0x02, // one entry per I/O APIC
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MPIOINTR = 0x03, // one entry per bus interrupt source
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MPLINTR = 0x04, // one entry per system interrupt source
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MPSASM = 0x80,
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MPHIERARCHY = 0x81,
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MPCBASM = 0x82,
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// PCMPprocessor and PCMPioapic flags
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MPEN = 0x01, // enabled
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MPBP = 0x02, // bootstrap processor
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// PCMPiointr and PCMPlintr flags
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MPPOMASK = 0x03, // polarity conforms to bus specs
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MPHIGH = 0x01, // active high
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MPLOW = 0x03, // active low
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MPELMASK = 0x0C, // trigger mode of APIC input signals
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MPEDGE = 0x04, // edge-triggered
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MPLEVEL = 0x0C, // level-triggered
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// PCMPiointr and PCMPlintr interrupt type
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MPINT = 0x00, // vectored interrupt from APIC Rdt
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MPNMI = 0x01, // non-maskable interrupt
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MPSMI = 0x02, // system management interrupt
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MPExtINT = 0x03, // vectored interrupt from external PIC
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};
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// Common bits for
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// I/O APIC Redirection Table Entry;
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// Local APIC Local Interrupt Vector Table;
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// Local APIC Inter-Processor Interrupt;
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// Local APIC Timer Vector Table.
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enum {
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APIC_FIXED = 0x00000000, // [10:8] Delivery Mode
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APIC_LOWEST = 0x00000100, // Lowest priority
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APIC_SMI = 0x00000200, // System Management Interrupt
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APIC_RR = 0x00000300, // Remote Read
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APIC_NMI = 0x00000400,
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APIC_INIT = 0x00000500, // INIT/RESET
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APIC_STARTUP = 0x00000600, // Startup IPI
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APIC_EXTINT = 0x00000700,
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APIC_PHYSICAL = 0x00000000, // [11] Destination Mode (RW)
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APIC_LOGICAL = 0x00000800,
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APIC_DELIVS = 0x00001000, // [12] Delivery Status (RO)
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APIC_HIGH = 0x00000000, // [13] Interrupt Input Pin Polarity (RW)
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APIC_LOW = 0x00002000,
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APIC_REMOTEIRR = 0x00004000, // [14] Remote IRR (RO)
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APIC_EDGE = 0x00000000, // [15] Trigger Mode (RW)
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APIC_LEVEL = 0x00008000,
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APIC_IMASK = 0x00010000, // [16] Interrupt Mask
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};
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