Clean up lapic code.
One initialization function now, not three. Use #defines instead of enums (consistent with other code, but sigh). Still boots in Bochs in SMP mode.
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rsc
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112873bc65
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b63bb0fd00
3 changed files with 115 additions and 169 deletions
4
defs.h
4
defs.h
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@ -69,12 +69,12 @@ void kinit(void);
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// lapic.c
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int cpu(void);
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extern uint* lapicaddr;
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extern volatile uint* lapic;
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void lapic_disableintr(void);
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void lapic_enableintr(void);
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void lapic_eoi(void);
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void lapic_init(int);
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void lapic_startap(uchar, int);
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void lapic_startap(uchar, uint);
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void lapic_timerinit(void);
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void lapic_timerintr(void);
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262
lapic.c
262
lapic.c
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@ -6,210 +6,162 @@
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#include "traps.h"
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#include "mmu.h"
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#include "proc.h"
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#include "lapic.h"
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enum { // Local APIC registers
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LAPIC_ID = 0x0020, // ID
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LAPIC_VER = 0x0030, // Version
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LAPIC_TPR = 0x0080, // Task Priority
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LAPIC_APR = 0x0090, // Arbitration Priority
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LAPIC_PPR = 0x00A0, // Processor Priority
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LAPIC_EOI = 0x00B0, // EOI
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LAPIC_LDR = 0x00D0, // Logical Destination
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LAPIC_DFR = 0x00E0, // Destination Format
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LAPIC_SVR = 0x00F0, // Spurious Interrupt Vector
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LAPIC_ISR = 0x0100, // Interrupt Status (8 registers)
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LAPIC_TMR = 0x0180, // Trigger Mode (8 registers)
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LAPIC_IRR = 0x0200, // Interrupt Request (8 registers)
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LAPIC_ESR = 0x0280, // Error Status
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LAPIC_ICRLO = 0x0300, // Interrupt Command
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LAPIC_ICRHI = 0x0310, // Interrupt Command [63:32]
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LAPIC_TIMER = 0x0320, // Local Vector Table 0 (TIMER)
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LAPIC_PCINT = 0x0340, // Performance Counter LVT
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LAPIC_LINT0 = 0x0350, // Local Vector Table 1 (LINT0)
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LAPIC_LINT1 = 0x0360, // Local Vector Table 2 (LINT1)
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LAPIC_ERROR = 0x0370, // Local Vector Table 3 (ERROR)
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LAPIC_TICR = 0x0380, // Timer Initial Count
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LAPIC_TCCR = 0x0390, // Timer Current Count
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LAPIC_TDCR = 0x03E0, // Timer Divide Configuration
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};
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// Local APIC registers, divided by 4 for use as uint[] indices.
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#define ID (0x0020/4) // ID
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#define VER (0x0030/4) // Version
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#define TPR (0x0080/4) // Task Priority
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#define APR (0x0090/4) // Arbitration Priority
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#define PPR (0x00A0/4) // Processor Priority
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#define EOI (0x00B0/4) // EOI
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#define LDR (0x00D0/4) // Logical Destination
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#define DFR (0x00E0/4) // Destination Format
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#define SVR (0x00F0/4) // Spurious Interrupt Vector
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#define ISR (0x0100/4) // Interrupt Status (8 registers)
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#define TMR (0x0180/4) // Trigger Mode (8 registers)
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#define IRR (0x0200/4) // Interrupt Request (8 registers)
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#define ESR (0x0280/4) // Error Status
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#define ICRLO (0x0300/4) // Interrupt Command
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#define ICRHI (0x0310/4) // Interrupt Command [63:32]
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#define TIMER (0x0320/4) // Local Vector Table 0 (TIMER)
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#define PCINT (0x0340/4) // Performance Counter LVT
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#define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0)
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#define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1)
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#define ERROR (0x0370/4) // Local Vector Table 3 (ERROR)
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#define TICR (0x0380/4) // Timer Initial Count
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#define TCCR (0x0390/4) // Timer Current Count
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#define TDCR (0x03E0/4) // Timer Divide Configuration
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enum { // LAPIC_SVR
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LAPIC_ENABLE = 0x00000100, // Unit Enable
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LAPIC_FOCUS = 0x00000200, // Focus Processor Checking Disable
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};
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// SVR
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#define ENABLE 0x00000100 // Unit Enable
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#define FOCUS 0x00000200 // Focus Processor Checking Disable
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enum { // LAPIC_ICRLO
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// ICRLO
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// [14] IPI Trigger Mode Level (RW)
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LAPIC_DEASSERT = 0x00000000, // Deassert level-sensitive interrupt
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LAPIC_ASSERT = 0x00004000, // Assert level-sensitive interrupt
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#define DEASSERT 0x00000000 // Deassert level-sensitive interrupt
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#define ASSERT 0x00004000 // Assert level-sensitive interrupt
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// [17:16] Remote Read Status
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LAPIC_INVALID = 0x00000000, // Invalid
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LAPIC_WAIT = 0x00010000, // In-Progress
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LAPIC_VALID = 0x00020000, // Valid
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#define INVALID 0x00000000 // Invalid
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#define WAIT 0x00010000 // In-Progress
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#define VALID 0x00020000 // Valid
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// [19:18] Destination Shorthand
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LAPIC_FIELD = 0x00000000, // No shorthand
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LAPIC_SELF = 0x00040000, // Self is single destination
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LAPIC_ALLINC = 0x00080000, // All including self
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LAPIC_ALLEXC = 0x000C0000, // All Excluding self
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};
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#define FIELD 0x00000000 // No shorthand
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#define SELF 0x00040000 // Self is single destination
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#define ALLINC 0x00080000 // All including self
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#define ALLEXC 0x000C0000 // All Excluding self
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enum { // LAPIC_ESR
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LAPIC_SENDCS = 0x00000001, // Send CS Error
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LAPIC_RCVCS = 0x00000002, // Receive CS Error
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LAPIC_SENDACCEPT = 0x00000004, // Send Accept Error
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LAPIC_RCVACCEPT = 0x00000008, // Receive Accept Error
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LAPIC_SENDVECTOR = 0x00000020, // Send Illegal Vector
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LAPIC_RCVVECTOR = 0x00000040, // Receive Illegal Vector
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LAPIC_REGISTER = 0x00000080, // Illegal Register Address
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};
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// ESR
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#define SENDCS 0x00000001 // Send CS Error
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#define RCVCS 0x00000002 // Receive CS Error
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#define SENDACCEPT 0x00000004 // Send Accept Error
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#define RCVACCEPT 0x00000008 // Receive Accept Error
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#define SENDVECTOR 0x00000020 // Send Illegal Vector
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#define RCVVECTOR 0x00000040 // Receive Illegal Vector
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#define REGISTER 0x00000080 // Illegal Register Address
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enum { // LAPIC_TIMER
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// [17] Timer Mode (RW)
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LAPIC_ONESHOT = 0x00000000, // One-shot
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LAPIC_PERIODIC = 0x00020000, // Periodic
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#define ONESHOT 0x00000000 // One-shot
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#define PERIODIC 0x00020000 // Periodic
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// [19:18] Timer Base (RW)
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LAPIC_CLKIN = 0x00000000, // use CLKIN as input
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LAPIC_TMBASE = 0x00040000, // use TMBASE
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LAPIC_DIVIDER = 0x00080000, // use output of the divider
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};
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#define CLKIN 0x00000000 // use CLKIN as input
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#define TMBASE 0x00040000 // use TMBASE
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#define DIVIDER 0x00080000 // use output of the divider
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enum { // LAPIC_TDCR
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LAPIC_X2 = 0x00000000, // divide by 2
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LAPIC_X4 = 0x00000001, // divide by 4
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LAPIC_X8 = 0x00000002, // divide by 8
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LAPIC_X16 = 0x00000003, // divide by 16
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LAPIC_X32 = 0x00000008, // divide by 32
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LAPIC_X64 = 0x00000009, // divide by 64
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LAPIC_X128 = 0x0000000A, // divide by 128
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LAPIC_X1 = 0x0000000B, // divide by 1
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};
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#define X2 0x00000000 // divide by 2
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#define X4 0x00000001 // divide by 4
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#define X8 0x00000002 // divide by 8
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#define X16 0x00000003 // divide by 16
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#define X32 0x00000008 // divide by 32
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#define X64 0x00000009 // divide by 64
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#define X128 0x0000000A // divide by 128
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#define X1 0x0000000B // divide by 1
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uint *lapicaddr;
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static int
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lapic_read(int r)
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{
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return *(lapicaddr+(r/sizeof(*lapicaddr)));
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}
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static void
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lapic_write(int r, int data)
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{
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*(lapicaddr+(r/sizeof(*lapicaddr))) = data;
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}
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void
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lapic_timerinit(void)
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{
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if(!lapicaddr)
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return;
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lapic_write(LAPIC_TDCR, LAPIC_X1);
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lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC |
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(IRQ_OFFSET + IRQ_TIMER));
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lapic_write(LAPIC_TCCR, 10000000);
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lapic_write(LAPIC_TICR, 10000000);
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}
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void
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lapic_timerintr(void)
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{
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if(lapicaddr)
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lapic_write(LAPIC_EOI, 0);
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}
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//PAGEBREAK!
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volatile uint *lapic; // Initialized in mp.c
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void
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lapic_init(int c)
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{
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uint r, lvt;
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if(!lapicaddr)
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if(!lapic)
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return;
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lapic_write(LAPIC_DFR, 0xFFFFFFFF); // Set dst format register
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r = (lapic_read(LAPIC_ID)>>24) & 0xFF; // Read APIC ID
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lapic_write(LAPIC_LDR, (1<<r)<<24); // Set logical dst register to r
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lapic_write(LAPIC_TPR, 0xFF); // No interrupts for now
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lapic[DFR] = 0xFFFFFFFF; // Set dst format register
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r = (lapic[ID]>>24) & 0xFF; // Read APIC ID
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lapic[LDR] = (1<<r) << 24;
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lapic[TPR] = 0xFF; // No interrupts for now
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// Enable APIC
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lapic_write(LAPIC_SVR, LAPIC_ENABLE|(IRQ_OFFSET+IRQ_SPURIOUS));
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lapic[SVR] = ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS);
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// In virtual wire mode, set up the LINT0 and LINT1 as follows:
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lapic_write(LAPIC_LINT0, APIC_IMASK | APIC_EXTINT);
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lapic_write(LAPIC_LINT1, APIC_IMASK | APIC_NMI);
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lapic[LINT0] = APIC_IMASK | APIC_EXTINT;
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lapic[LINT1] = APIC_IMASK | APIC_NMI;
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lapic_write(LAPIC_EOI, 0); // Ack any outstanding interrupts.
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lapic[EOI] = 0; // Ack any outstanding interrupts.
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lvt = (lapic_read(LAPIC_VER)>>16) & 0xFF;
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lvt = (lapic[VER]>>16) & 0xFF;
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if(lvt >= 4)
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lapic_write(LAPIC_PCINT, APIC_IMASK);
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lapic_write(LAPIC_ERROR, IRQ_OFFSET+IRQ_ERROR);
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lapic_write(LAPIC_ESR, 0);
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lapic_read(LAPIC_ESR);
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lapic[PCINT] = APIC_IMASK;
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lapic[ERROR] = IRQ_OFFSET+IRQ_ERROR;
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lapic[ESR] = 0;
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lapic[ESR];
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// Issue an INIT Level De-Assert to synchronise arbitration ID's.
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lapic_write(LAPIC_ICRHI, 0);
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lapic_write(LAPIC_ICRLO, LAPIC_ALLINC|APIC_LEVEL|
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LAPIC_DEASSERT|APIC_INIT);
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while(lapic_read(LAPIC_ICRLO) & APIC_DELIVS)
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lapic[ICRHI] = 0;
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lapic[ICRLO] = ALLINC | APIC_LEVEL |
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DEASSERT | APIC_INIT;
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while(lapic[ICRLO] & APIC_DELIVS)
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;
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}
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void
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lapic_enableintr(void)
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{
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if(lapicaddr)
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lapic_write(LAPIC_TPR, 0);
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}
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// Initialize the interrupt timer.
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// On real hardware would need to do more XXX.
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lapic[TDCR] = X1;
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lapic[TIMER] = CLKIN | PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
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lapic[TCCR] = 10000000;
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lapic[TICR] = 10000000;
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void
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lapic_disableintr(void)
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{
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if(lapicaddr)
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lapic_write(LAPIC_TPR, 0xFF);
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}
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void
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lapic_eoi(void)
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{
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if(lapicaddr)
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lapic_write(LAPIC_EOI, 0);
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// Enable interrupts on the APIC (but not on processor).
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lapic[TPR] = 0;
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}
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int
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cpu(void)
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{
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int x;
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if(lapicaddr)
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x = (lapic_read(LAPIC_ID)>>24) & 0xFF;
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else
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x = 0;
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return x;
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if(lapic)
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return lapic[ID]>>24;
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return 0;
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}
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// Acknowledge interrupt.
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void
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lapic_startap(uchar apicid, int v)
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lapic_eoi(void)
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{
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int crhi, i;
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if(lapic)
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lapic[EOI] = 0;
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}
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// Start additional processor running bootstrap code at addr.
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void
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lapic_startap(uchar apicid, uint addr)
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{
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int i;
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volatile int j = 0;
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crhi = apicid<<24;
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|
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LAPIC_ASSERT|APIC_INIT);
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = FIELD | APIC_LEVEL | ASSERT | APIC_INIT;
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for(j=0; j<10000; j++); // 200us
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|
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LAPIC_DEASSERT|APIC_INIT);
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lapic[ICRLO] = FIELD | APIC_LEVEL | DEASSERT | APIC_INIT;
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for(j=0; j<1000000; j++); // 10ms
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// in p9 code, this was i < 2, which is what the spec says on page B-3
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for(i = 0; i < 1; i++){
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_EDGE|APIC_STARTUP|(v/4096));
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for(i = 0; i < 2; i++){
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = FIELD | APIC_EDGE | APIC_STARTUP | (addr/4096);
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for(j=0; j<10000; j++); // 200us
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}
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}
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8
main.c
8
main.c
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@ -37,7 +37,6 @@ main0(void)
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asm volatile("movl %0, %%ebp" : : "r" (cpus[bcpu].mpstack+MPSTACK));
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lapic_init(bcpu);
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cprintf("\ncpu%d: starting xv6\n\n", cpu());
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pinit(); // process table
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@ -53,10 +52,7 @@ main0(void)
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console_init(); // I/O devices & their interrupts
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ide_init(); // disk
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mp_startthem(); // other CPUs
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if(ismp){
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lapic_timerinit(); // smp timer
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lapic_enableintr(); // local interrupts
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}else
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if(!ismp)
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pit8253_timerinit(); // uniprocessor timer
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userinit(); // first user process
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@ -74,8 +70,6 @@ mpmain(void)
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cprintf("cpu%d: starting\n", cpu());
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idtinit();
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lapic_init(cpu());
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lapic_timerinit();
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lapic_enableintr();
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setupsegs(0);
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cpuid(0, 0, 0, 0, 0); // memory barrier
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