2006-07-12 19:19:24 +02:00
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#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "traps.h"
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#include "mmu.h"
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#include "proc.h"
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2006-09-06 19:53:15 +02:00
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enum { // Local APIC registers
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LAPIC_ID = 0x0020, // ID
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LAPIC_VER = 0x0030, // Version
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LAPIC_TPR = 0x0080, // Task Priority
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LAPIC_APR = 0x0090, // Arbitration Priority
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LAPIC_PPR = 0x00A0, // Processor Priority
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LAPIC_EOI = 0x00B0, // EOI
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LAPIC_LDR = 0x00D0, // Logical Destination
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LAPIC_DFR = 0x00E0, // Destination Format
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LAPIC_SVR = 0x00F0, // Spurious Interrupt Vector
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LAPIC_ISR = 0x0100, // Interrupt Status (8 registers)
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LAPIC_TMR = 0x0180, // Trigger Mode (8 registers)
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LAPIC_IRR = 0x0200, // Interrupt Request (8 registers)
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LAPIC_ESR = 0x0280, // Error Status
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LAPIC_ICRLO = 0x0300, // Interrupt Command
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LAPIC_ICRHI = 0x0310, // Interrupt Command [63:32]
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LAPIC_TIMER = 0x0320, // Local Vector Table 0 (TIMER)
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LAPIC_PCINT = 0x0340, // Performance Counter LVT
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LAPIC_LINT0 = 0x0350, // Local Vector Table 1 (LINT0)
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LAPIC_LINT1 = 0x0360, // Local Vector Table 2 (LINT1)
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LAPIC_ERROR = 0x0370, // Local Vector Table 3 (ERROR)
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LAPIC_TICR = 0x0380, // Timer Initial Count
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LAPIC_TCCR = 0x0390, // Timer Current Count
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LAPIC_TDCR = 0x03E0, // Timer Divide Configuration
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2006-07-12 19:19:24 +02:00
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};
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2006-09-06 19:53:15 +02:00
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enum { // LAPIC_SVR
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LAPIC_ENABLE = 0x00000100, // Unit Enable
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LAPIC_FOCUS = 0x00000200, // Focus Processor Checking Disable
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2006-07-12 19:19:24 +02:00
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};
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2006-09-06 19:53:15 +02:00
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enum { // LAPIC_ICRLO
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// [14] IPI Trigger Mode Level (RW)
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LAPIC_DEASSERT = 0x00000000, // Deassert level-sensitive interrupt
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LAPIC_ASSERT = 0x00004000, // Assert level-sensitive interrupt
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2006-09-06 19:50:20 +02:00
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// [17:16] Remote Read Status
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2006-09-06 19:53:15 +02:00
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LAPIC_INVALID = 0x00000000, // Invalid
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LAPIC_WAIT = 0x00010000, // In-Progress
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LAPIC_VALID = 0x00020000, // Valid
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2006-09-06 19:50:20 +02:00
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// [19:18] Destination Shorthand
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2006-09-06 19:53:15 +02:00
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LAPIC_FIELD = 0x00000000, // No shorthand
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LAPIC_SELF = 0x00040000, // Self is single destination
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LAPIC_ALLINC = 0x00080000, // All including self
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LAPIC_ALLEXC = 0x000C0000, // All Excluding self
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2006-07-12 19:19:24 +02:00
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};
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2006-09-06 19:53:15 +02:00
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enum { // LAPIC_ESR
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LAPIC_SENDCS = 0x00000001, // Send CS Error
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LAPIC_RCVCS = 0x00000002, // Receive CS Error
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LAPIC_SENDACCEPT = 0x00000004, // Send Accept Error
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LAPIC_RCVACCEPT = 0x00000008, // Receive Accept Error
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LAPIC_SENDVECTOR = 0x00000020, // Send Illegal Vector
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LAPIC_RCVVECTOR = 0x00000040, // Receive Illegal Vector
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LAPIC_REGISTER = 0x00000080, // Illegal Register Address
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};
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2006-09-06 19:53:15 +02:00
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enum { // LAPIC_TIMER
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// [17] Timer Mode (RW)
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LAPIC_ONESHOT = 0x00000000, // One-shot
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LAPIC_PERIODIC = 0x00020000, // Periodic
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2006-07-12 19:19:24 +02:00
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2006-09-06 19:50:20 +02:00
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// [19:18] Timer Base (RW)
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LAPIC_CLKIN = 0x00000000, // use CLKIN as input
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LAPIC_TMBASE = 0x00040000, // use TMBASE
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LAPIC_DIVIDER = 0x00080000, // use output of the divider
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};
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enum { // LAPIC_TDCR
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LAPIC_X2 = 0x00000000, // divide by 2
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LAPIC_X4 = 0x00000001, // divide by 4
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LAPIC_X8 = 0x00000002, // divide by 8
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LAPIC_X16 = 0x00000003, // divide by 16
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LAPIC_X32 = 0x00000008, // divide by 32
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LAPIC_X64 = 0x00000009, // divide by 64
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LAPIC_X128 = 0x0000000A, // divide by 128
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LAPIC_X1 = 0x0000000B, // divide by 1
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2006-07-12 19:19:24 +02:00
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};
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2006-07-20 11:07:53 +02:00
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uint *lapicaddr;
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2006-07-12 19:19:24 +02:00
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static int
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lapic_read(int r)
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{
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return *(lapicaddr+(r/sizeof(*lapicaddr)));
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}
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static void
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lapic_write(int r, int data)
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{
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*(lapicaddr+(r/sizeof(*lapicaddr))) = data;
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}
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void
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2006-07-17 03:25:22 +02:00
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lapic_timerinit(void)
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2006-07-12 19:19:24 +02:00
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{
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lapic_write(LAPIC_TDCR, LAPIC_X1);
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC |
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(IRQ_OFFSET + IRQ_TIMER));
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2006-07-12 19:19:24 +02:00
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lapic_write(LAPIC_TCCR, 10000000);
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lapic_write(LAPIC_TICR, 10000000);
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}
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void
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2006-07-17 03:25:22 +02:00
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lapic_timerintr(void)
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2006-07-12 19:19:24 +02:00
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{
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2006-09-06 19:27:19 +02:00
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lapic_write(LAPIC_EOI, 0);
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2006-07-12 19:19:24 +02:00
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}
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void
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lapic_init(int c)
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{
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2006-07-20 11:07:53 +02:00
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uint r, lvt;
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2006-07-12 19:19:24 +02:00
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_DFR, 0xFFFFFFFF); // Set dst format register
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r = (lapic_read(LAPIC_ID)>>24) & 0xFF; // Read APIC ID
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lapic_write(LAPIC_LDR, (1<<r)<<24); // Set logical dst register to r
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lapic_write(LAPIC_TPR, 0xFF); // No interrupts for now
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// Enable APIC
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lapic_write(LAPIC_SVR, LAPIC_ENABLE|(IRQ_OFFSET+IRQ_SPURIOUS));
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2006-07-12 19:19:24 +02:00
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2006-09-06 19:50:20 +02:00
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// In virtual wire mode, set up the LINT0 and LINT1 as follows:
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2006-07-12 19:19:24 +02:00
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lapic_write(LAPIC_LINT0, APIC_IMASK | APIC_EXTINT);
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lapic_write(LAPIC_LINT1, APIC_IMASK | APIC_NMI);
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_EOI, 0); // Ack any outstanding interrupts.
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2006-07-12 19:19:24 +02:00
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lvt = (lapic_read(LAPIC_VER)>>16) & 0xFF;
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if(lvt >= 4)
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lapic_write(LAPIC_PCINT, APIC_IMASK);
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lapic_write(LAPIC_ERROR, IRQ_OFFSET+IRQ_ERROR);
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lapic_write(LAPIC_ESR, 0);
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lapic_read(LAPIC_ESR);
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2006-09-06 19:50:20 +02:00
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// Issue an INIT Level De-Assert to synchronise arbitration ID's.
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2006-07-12 19:19:24 +02:00
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lapic_write(LAPIC_ICRHI, 0);
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_ICRLO, LAPIC_ALLINC|APIC_LEVEL|
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LAPIC_DEASSERT|APIC_INIT);
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2006-07-12 19:19:24 +02:00
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while(lapic_read(LAPIC_ICRLO) & APIC_DELIVS)
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;
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}
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void
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2006-09-06 19:27:19 +02:00
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lapic_enableintr(void)
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2006-07-12 19:19:24 +02:00
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{
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lapic_write(LAPIC_TPR, 0);
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}
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void
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2006-09-06 19:27:19 +02:00
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lapic_disableintr(void)
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2006-07-12 19:19:24 +02:00
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{
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lapic_write(LAPIC_TPR, 0xFF);
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}
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2006-08-04 20:12:31 +02:00
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void
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lapic_eoi(void)
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{
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2006-09-06 19:27:19 +02:00
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lapic_write(LAPIC_EOI, 0);
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2006-08-04 20:12:31 +02:00
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}
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2006-07-12 19:19:24 +02:00
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int
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cpu(void)
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{
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2006-08-08 21:58:06 +02:00
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int x = (lapic_read(LAPIC_ID)>>24) & 0xFF;
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return x;
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2006-07-12 19:19:24 +02:00
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}
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void
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2006-07-20 11:07:53 +02:00
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lapic_startap(uchar apicid, int v)
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{
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int crhi, i;
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volatile int j = 0;
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crhi = apicid<<24;
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lapic_write(LAPIC_ICRHI, crhi);
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|
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LAPIC_ASSERT|APIC_INIT);
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2006-07-12 19:19:24 +02:00
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2006-09-06 19:27:19 +02:00
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while(j++ < 10000) {;}
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2006-09-06 21:08:14 +02:00
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|
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LAPIC_DEASSERT|APIC_INIT);
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2006-07-12 19:19:24 +02:00
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2006-09-06 19:27:19 +02:00
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while(j++ < 1000000) {;}
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2006-07-12 19:19:24 +02:00
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// in p9 code, this was i < 2, which is what the spec says on page B-3
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for(i = 0; i < 1; i++){
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lapic_write(LAPIC_ICRHI, crhi);
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2006-08-29 21:06:37 +02:00
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_EDGE|APIC_STARTUP|(v/4096));
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2006-09-06 19:27:19 +02:00
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while(j++ < 100000) {;}
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}
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}
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