Kees Jongenburger d77debb5b7 arm:caching access the l1 pages over cacheable memory. ... When we start using a new pagetable (for a new process) the last part is to ensure the pagetable itself can be accessed by VM. This is done in pt_bind by updating the "pagetable of pagetables" and we want this mapping to match other mappings to the l1 pagetable. Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d		2013-09-26 11:57:44 +02:00
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earm	arm:vm header cleanup.	2013-05-16 20:39:19 +02:00
i386	arm:caching access the l1 pages over cacheable memory.	2013-09-26 11:57:44 +02:00