arm:caching access the l1 pages over cacheable memory.

When we start using a new pagetable (for a new process)
the last part is to ensure the pagetable itself can be
accessed by VM. This is done in pt_bind by updating
the "pagetable of pagetables" and we want this mapping
to match other mappings to the l1 pagetable.

Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d

servers/vm/arch/i386/pagetable.c

@@ -1324,6 +1324,7 @@ int pt_bind(pt_t *pt, struct vmproc *who)
 			(phys+i*VM_PAGE_SIZE)
 			| ARCH_VM_PTE_PRESENT
 			| ARCH_VM_PTE_RW
+			| ARM_VM_PTE_CACHED
 			| ARCH_VM_PTE_USER; //LSC FIXME
 	}
 }