6 commits

Author	SHA1	Message	Date
Ben Gras	8e7c0604bd	arm timer fix ... . set 'done' once initialized so 32-bit read frc works, thanks to keesj . make sure the software-implemented upper 32 bit of the 64-bit "tsc" value works OK by adding an assert in one of its calls Change-Id: I5ce24fea919f4610c6a86ac7ec9f04b1815620c2	2013-06-19 13:11:32 +02:00
Kees Jongenburger	a5a693a046	arm:no longer rely on a 1:1 phys mapping for device memory. ... Change-Id: Ie3f61069f882c37dbb81dee813fdfd883e7468cf	2013-06-12 16:42:12 +02:00
Kees Jongenburger	3139ce9631	arm:omap timers remove hardcoded base address. ... Omap timers remove hardcoded base address and add some initial support for the beaglebone's timers. Frclock_util will need refactoring to remain independent of the ARM flavour. Change-Id: I2b5d04e930364262c81b5686de634c0a51796b23	2013-05-24 14:03:14 +02:00
Ben Gras	8ea66915f2	kernel: scheduling fix for ARM ... . make read_tsc_64 use the free-running clock, significantly improving scheduling behaviour Change-Id: Idf6a12f6e26be7fe3b3664c278cae846d8b2a442	2013-02-03 22:49:05 +01:00
Thomas Veerman	db8c1ee9d0	ARM: provide free running clock to replace ccnt ... The Cycle CouNTer on ARM cannot be used reliably as it wraps around rather quickly and can be altered by user space (on Minix). Furthermore, it's buggy when wrapping and is not implemented at all on the Linaro Beagleboard emulator. This patch programs GPTIMER10 as a free running clock at 1.625 MHz (it doesn't generate interrupts). It's memory mapped into every process, which enables libsys to provide micro_delay(). Change-Id: Iba004c6c62976762fe154ea390d69e518eec1531	2013-01-31 15:19:11 +00:00
Lionel Sambuc	b1c4ba4ab6	ARM updates ... Due to the ABI we are using we have to use the earm architecture moniker for the build system to behave correctly. This involves then some headers to move around. There is also a few related Makefile updates as well as minor source code corrections.	2013-01-17 10:03:58 +01:00

Renamed from kernel/arch/arm/omap_timer.c (Browse further)