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arm am335x: disable watchdog timer on bootup

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. for new uboot (specifically beaglebone black rev c) compliance

Change-Id: I28fd0ca15f5365e14bf2bb9407f266e3e570b6d9
This commit is contained in:
Ben Gras 2014-08-22 14:06:57 +02:00 committed by Ben Gras
parent 2909efcb88
commit 222afb38ac
4 changed files with 19 additions and 1 deletions
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1
minix/kernel/arch/earm/bsp/include/bsp_reset.h
View file

@ -4,5 +4,6 @@
void bsp_reset_init(void); void bsp_reset_init(void);
void bsp_reset(void); void bsp_reset(void);
void bsp_poweroff(void); void bsp_poweroff(void);
void bsp_disable_watchdog(void);
#endif /* _BSP_RESET_H_ */ #endif /* _BSP_RESET_H_ */

3
minix/kernel/arch/earm/bsp/ti/omap_init.c
View file

@ -15,4 +15,7 @@ bsp_init()
/* map memory for reset control */ /* map memory for reset control */
bsp_reset_init(); bsp_reset_init();
/* disable watchdog */
bsp_disable_watchdog();
} }

12
minix/kernel/arch/earm/bsp/ti/omap_reset.c
View file

@ -12,6 +12,7 @@
#include "arch_proto.h" #include "arch_proto.h"
#include "bsp_reset.h" #include "bsp_reset.h"
#include "omap_timer_registers.h"
#include "omap_rtc.h" #include "omap_rtc.h"
#define AM335X_CM_BASE 0x44E00000 #define AM335X_CM_BASE 0x44E00000
@ -86,3 +87,14 @@ bsp_poweroff(void)
while (1); while (1);
} }
} }
void bsp_disable_watchdog(void)
{
if(BOARD_IS_BB(machine.board_id)) {
mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA);
while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555);
while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
}
}

4
minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h
View file

@ -65,7 +65,9 @@
#define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */ #define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */
#define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */ #define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */
#define AM335X_WDT_BASE 0x44E35000 /* watchdog timer */
#define AM335X_WDT_WWPS 0x34 /* command posted status */
#define AM335X_WDT_WSPR 0x48 /* activate/deactivate sequence */
/* Interrupt status register fields */ /* Interrupt status register fields */
#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ #define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */