diff --git a/minix/kernel/arch/earm/bsp/include/bsp_reset.h b/minix/kernel/arch/earm/bsp/include/bsp_reset.h
index 6158a8f84..7f91da13c 100644
--- a/minix/kernel/arch/earm/bsp/include/bsp_reset.h
+++ b/minix/kernel/arch/earm/bsp/include/bsp_reset.h
@@ -4,5 +4,6 @@
 void bsp_reset_init(void);
 void bsp_reset(void);
 void bsp_poweroff(void);
+void bsp_disable_watchdog(void);
 
 #endif /* _BSP_RESET_H_ */
diff --git a/minix/kernel/arch/earm/bsp/ti/omap_init.c b/minix/kernel/arch/earm/bsp/ti/omap_init.c
index 1d54bfeca..99a47b765 100644
--- a/minix/kernel/arch/earm/bsp/ti/omap_init.c
+++ b/minix/kernel/arch/earm/bsp/ti/omap_init.c
@@ -15,4 +15,7 @@ bsp_init()
 
 	/* map memory for reset control */
 	bsp_reset_init();
+
+	/* disable watchdog */
+	bsp_disable_watchdog();
 }
diff --git a/minix/kernel/arch/earm/bsp/ti/omap_reset.c b/minix/kernel/arch/earm/bsp/ti/omap_reset.c
index 13daa5a59..db8562657 100644
--- a/minix/kernel/arch/earm/bsp/ti/omap_reset.c
+++ b/minix/kernel/arch/earm/bsp/ti/omap_reset.c
@@ -12,6 +12,7 @@
 #include "arch_proto.h"
 #include "bsp_reset.h"
 
+#include "omap_timer_registers.h"
 #include "omap_rtc.h"
 
 #define AM335X_CM_BASE 0x44E00000
@@ -86,3 +87,14 @@ bsp_poweroff(void)
 		while (1);
 	}
 }
+
+void bsp_disable_watchdog(void)
+{
+        if(BOARD_IS_BB(machine.board_id)) {
+		mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA);
+		while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+		mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555);
+		while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+	}
+}
+
diff --git a/minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h b/minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h
index 619272da8..b127e48ed 100644
--- a/minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h
+++ b/minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h
@@ -65,7 +65,9 @@
 #define AM335X_TIMER_TSICR     0x054 /* Control posted mode and functional SW reset */
 #define AM335X_TIMER_TCAR2     0x058 /* Second captured value of counter register */
 
-
+#define AM335X_WDT_BASE		0x44E35000	/* watchdog timer */
+#define AM335X_WDT_WWPS		0x34		/* command posted status */
+#define AM335X_WDT_WSPR		0x48		/* activate/deactivate sequence */
 
 /* Interrupt status register fields */
 #define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */