2012-10-08 03:38:03 +02:00
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#ifndef _ARM_CPUFUNC_H
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#define _ARM_CPUFUNC_H
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2013-02-15 01:07:04 +01:00
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#if 0
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/* check interrupt state */
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static inline void check_int(unsigned int state, int line)
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{
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unsigned int cpsr = 0;
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asm volatile("mrs %0, cpsr" : "=r" (cpsr));
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if ((cpsr & PSR_F) != (state & PSR_F))
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printf("%d: FIQs are unexpectedly %s\n", line, (cpsr & PSR_F) ? "MASKED" : "UNMASKED");
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if ((cpsr & PSR_I) != (state & PSR_I))
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printf("%d: IRQs are unexpectedly %s\n", line, (cpsr & PSR_I) ? "MASKED" : "UNMASKED");
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}
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#endif
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2012-10-08 03:38:03 +02:00
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/* Data memory barrier */
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static inline void dmb(void)
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{
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asm volatile("dmb" : : : "memory");
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}
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/* Data synchronization barrier */
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static inline void dsb(void)
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{
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asm volatile("dsb" : : : "memory");
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}
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/* Instruction synchronization barrier */
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static inline void isb(void)
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{
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asm volatile("isb" : : : "memory");
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}
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static inline void barrier(void)
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{
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dsb();
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isb();
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}
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2013-09-25 10:53:41 +02:00
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/* Read CLIDR, Cache Level ID Register */
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static inline u32_t read_clidr(){
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u32_t clidr;
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asm volatile("mrc p15, 1, %[clidr], c0, c0 , 1 @ READ CLIDR\n\t"
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: [clidr] "=r" (clidr));
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return clidr;
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}
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/* Read CSSELR, Cache Size Selection Register */
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static inline u32_t read_csselr(){
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u32_t csselr;
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asm volatile("mrc p15, 2, %[csselr], c0, c0 , 0 @ READ CSSELR\n\t"
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: [csselr] "=r" (csselr));
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return csselr;
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}
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/* Write CSSELR, Cache Size Selection Register */
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static inline void write_csselr(u32_t csselr){
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asm volatile("mcr p15, 2, %[csselr], c0, c0 , 0 @ WRITE CSSELR\n\t"
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: : [csselr] "r" (csselr));
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}
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/* Read Cache Size ID Register */
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static inline u32_t read_ccsidr()
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{
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u32_t ccsidr;
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asm volatile("mrc p15, 1, %[ccsidr], c0, c0, 0 @ Read CCSIDR\n\t"
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: [ccsidr] "=r" (ccsidr));
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return ccsidr;
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}
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/* Read TLBTR, TLB Type Register */
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static inline u32_t read_tlbtr()
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{
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u32_t tlbtr;
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asm volatile("mrc p15, 0, %[tlbtr], c0, c0, 3 @ Read TLBTR\n\t"
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: [tlbtr] "=r" (tlbtr));
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return tlbtr;
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}
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/* keesj:move these out */
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static inline u32_t ilog2(u32_t t)
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{
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u32_t counter =0;
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while( (t = t >> 1) ) counter ++;
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return counter;
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}
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/* keesj:move these out */
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static inline u32_t ipow2(u32_t t)
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{
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return 1 << t;
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}
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/*
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* type = 1 == CLEAN
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* type = 2 == INVALIDATE
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*/
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static inline void dcache_maint(int type){
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u32_t cache_level ;
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u32_t clidr;
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u32_t ctype;
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u32_t ccsidr;
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u32_t line_size,line_length;
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u32_t number_of_sets,number_of_ways;
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u32_t set,way;
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clidr = read_clidr();
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u32_t loc = ( clidr >> 24) & 0x7;
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u32_t louu = ( clidr >> 27) & 0x7;
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u32_t louis = ( clidr >> 21) & 0x7;
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for (cache_level =0 ; cache_level < loc; cache_level++){
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/* get current cache type */
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ctype = ( clidr >> cache_level*3) & 0x7;
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/* select data or unified or cache level */
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write_csselr(cache_level << 1);
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isb();
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ccsidr = read_ccsidr();
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line_size = ccsidr & 0x7;
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line_length = 2 << (line_size + 1) ; /* 2**(line_size + 2) */
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number_of_sets = ((ccsidr >> 13) & 0x7fff) + 1;
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number_of_ways = ((ccsidr >> 3) & 0x3ff) + 1;
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u32_t way_bits = ilog2(number_of_ways);
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if(ipow2(ilog2(number_of_ways) < number_of_ways) ) {
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way_bits++;
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}
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u32_t l = ilog2(line_length);
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for (way =0 ; way < number_of_ways; way++) {
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for (set =0 ; set < number_of_sets; set++) {
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u32_t val = ( way << (32 - way_bits) ) | (set << l) | (cache_level << 1 );
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if (type == 1) {
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/* DCCISW, Data Cache Clean and Invalidate by Set/Way */
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asm volatile("mcr p15, 0, %[set], c7, c14, 2 @ DCCISW"
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: : [set] "r" (val));
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} else if (type ==2 ){
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/* DCISW, Data Cache Invalidate by Set/Way */
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asm volatile("mcr p15, 0, %[set], c7, c6, 2"
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: : [set] "r" (val));
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}
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}
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}
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}
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dsb();
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isb();
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}
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static inline void dcache_clean(){
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dcache_maint(1);
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}
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static inline void dcache_invalidate (){
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dcache_maint(2);
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}
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2012-10-08 03:38:03 +02:00
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static inline void refresh_tlb(void)
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{
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dsb();
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2013-02-15 01:07:04 +01:00
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2012-10-08 03:38:03 +02:00
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/* Invalidate entire unified TLB */
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" : : [zero] "r" (0));
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#if 0
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/* Invalidate entire data TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c6, 0" : : [zero] "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c5, 0" : : [zero] "r" (0));
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#endif
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile("mcr p15, 0, %[zero], c7, c5, 0" : : [zero] "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile("mcr p15, 0, %[zero], c7, c5, 6" : : [zero] "r" (0)); /* flush BTB */
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2012-10-08 03:38:03 +02:00
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dsb();
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isb();
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}
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/* Read System Control Register */
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static inline u32_t read_sctlr()
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{
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2013-02-15 01:07:04 +01:00
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u32_t ctl;
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2012-10-08 03:38:03 +02:00
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2013-02-15 01:07:04 +01:00
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asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
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: [ctl] "=r" (ctl));
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return ctl;
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2012-10-08 03:38:03 +02:00
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}
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/* Write System Control Register */
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static inline void write_sctlr(u32_t ctl)
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{
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
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: : [ctl] "r" (ctl));
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isb();
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2012-10-08 03:38:03 +02:00
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}
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/* Read Translation Table Base Register 0 */
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static inline u32_t read_ttbr0()
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{
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2013-02-15 01:07:04 +01:00
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u32_t bar;
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asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
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: [bar] "=r" (bar));
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2012-10-08 03:38:03 +02:00
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2013-09-25 11:12:46 +02:00
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return bar & ARM_TTBR_ADDR_MASK;
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2012-10-08 03:38:03 +02:00
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}
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/* Write Translation Table Base Register 0 */
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static inline void write_ttbr0(u32_t bar)
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{
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2013-02-15 01:07:04 +01:00
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barrier();
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2013-09-25 11:12:46 +02:00
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/* In our setup TTBR contains the base address *and* the flags
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but other pieces of the kernel code expect ttbr to be the
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base address of the l1 page table. We therefore add the
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flags here and remove them in the read_ttbr0 */
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u32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
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2013-09-25 11:12:46 +02:00
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: : [bar] "r" (v));
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2013-02-15 01:07:04 +01:00
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refresh_tlb();
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2012-10-08 03:38:03 +02:00
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}
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/* Reload Translation Table Base Register 0 */
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static inline void reload_ttbr0(void)
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{
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2013-02-15 01:07:04 +01:00
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reg_t ttbr = read_ttbr0();
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write_ttbr0(ttbr);
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2012-10-08 03:38:03 +02:00
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}
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/* Read Translation Table Base Register 1 */
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static inline u32_t read_ttbr1()
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{
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2013-02-15 01:07:04 +01:00
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u32_t bar;
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2012-10-08 03:38:03 +02:00
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2013-02-15 01:07:04 +01:00
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asm volatile("mrc p15, 0, %[bar], c2, c0, 1 @ Read TTBR1\n\t"
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: [bar] "=r" (bar));
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return bar;
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2012-10-08 03:38:03 +02:00
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}
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/* Write Translation Table Base Register 1 */
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static inline void write_ttbr1(u32_t bar)
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{
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2013-02-15 01:07:04 +01:00
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barrier();
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asm volatile("mcr p15, 0, %[bar], c2, c0, 1 @ Write TTBR1\n\t"
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: : [bar] "r" (bar));
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refresh_tlb();
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2012-10-08 03:38:03 +02:00
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}
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/* Reload Translation Table Base Register 1 */
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static inline void reload_ttbr1(void)
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{
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2013-02-15 01:07:04 +01:00
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reg_t ttbr = read_ttbr1();
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write_ttbr1(ttbr);
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2012-10-08 03:38:03 +02:00
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}
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/* Read Translation Table Base Control Register */
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static inline u32_t read_ttbcr()
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{
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2013-02-15 01:07:04 +01:00
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u32_t bcr;
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asm volatile("mrc p15, 0, %[bcr], c2, c0, 2 @ Read TTBCR\n\t"
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: [bcr] "=r" (bcr));
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2012-10-08 03:38:03 +02:00
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2013-02-15 01:07:04 +01:00
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return bcr;
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2012-10-08 03:38:03 +02:00
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}
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/* Write Translation Table Base Control Register */
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static inline void write_ttbcr(u32_t bcr)
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{
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
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: : [bcr] "r" (bcr));
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isb();
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2012-10-08 03:38:03 +02:00
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}
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/* Read Domain Access Control Register */
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static inline u32_t read_dacr()
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{
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2013-02-15 01:07:04 +01:00
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u32_t dacr;
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asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
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: [dacr] "=r" (dacr));
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2012-10-08 03:38:03 +02:00
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2013-02-15 01:07:04 +01:00
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return dacr;
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2012-10-08 03:38:03 +02:00
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}
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/* Write Domain Access Control Register */
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static inline void write_dacr(u32_t dacr)
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{
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
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: : [dacr] "r" (dacr));
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isb();
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2012-10-08 03:38:03 +02:00
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}
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/* Read Data Fault Status Register */
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static inline u32_t read_dfsr()
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{
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2013-02-15 01:07:04 +01:00
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u32_t fsr;
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asm volatile("mrc p15, 0, %[fsr], c5, c0, 0 @ Read DFSR\n\t"
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: [fsr] "=r" (fsr));
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2012-10-08 03:38:03 +02:00
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2013-02-15 01:07:04 +01:00
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return fsr;
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2012-10-08 03:38:03 +02:00
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}
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/* Write Data Fault Status Register */
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static inline void write_dfsr(u32_t fsr)
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{
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2013-02-15 01:07:04 +01:00
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asm volatile("mcr p15, 0, %[fsr], c5, c0, 0 @ Write DFSR\n\t"
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: : [fsr] "r" (fsr));
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isb();
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2012-10-08 03:38:03 +02:00
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}
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/* Read Instruction Fault Status Register */
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static inline u32_t read_ifsr()
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{
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2013-02-15 01:07:04 +01:00
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u32_t fsr;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[fsr], c5, c0, 1 @ Read IFSR\n\t"
|
|
|
|
: [fsr] "=r" (fsr));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return fsr;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Instruction Fault Status Register */
|
|
|
|
static inline void write_ifsr(u32_t fsr)
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("mcr p15, 0, %[fsr], c5, c0, 1 @ Write IFSR\n\t"
|
|
|
|
: : [fsr] "r" (fsr));
|
|
|
|
|
|
|
|
isb();
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read Data Fault Address Register */
|
|
|
|
static inline u32_t read_dfar()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t far;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[far], c6, c0, 0 @ Read DFAR\n\t"
|
|
|
|
: [far] "=r" (far));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return far;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Data Fault Address Register */
|
|
|
|
static inline void write_dfar(u32_t far)
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("mcr p15, 0, %[far], c6, c0, 0 @ Write DFAR\n\t"
|
|
|
|
: : [far] "r" (far));
|
|
|
|
|
|
|
|
isb();
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read Instruction Fault Address Register */
|
|
|
|
static inline u32_t read_ifar()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t far;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[far], c6, c0, 2 @ Read IFAR\n\t"
|
|
|
|
: [far] "=r" (far));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return far;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Instruction Fault Address Register */
|
|
|
|
static inline void write_ifar(u32_t far)
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("mcr p15, 0, %[far], c6, c0, 2 @ Write IFAR\n\t"
|
|
|
|
: : [far] "r" (far));
|
|
|
|
|
|
|
|
isb();
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read Vector Base Address Register */
|
|
|
|
static inline u32_t read_vbar()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t vbar;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[vbar], c12, c0, 0 @ Read VBAR\n\t"
|
|
|
|
: [vbar] "=r" (vbar));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return vbar;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Vector Base Address Register */
|
|
|
|
static inline void write_vbar(u32_t vbar)
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("mcr p15, 0, %[vbar], c12, c0, 0 @ Write VBAR\n\t"
|
|
|
|
: : [vbar] "r" (vbar));
|
|
|
|
|
|
|
|
isb();
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the Main ID Register */
|
|
|
|
static inline u32_t read_midr()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t id;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[id], c0, c0, 0 @ read MIDR\n\t"
|
|
|
|
: [id] "=r" (id));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return id;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read Auxiliary Control Register */
|
|
|
|
static inline u32_t read_actlr()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t ctl;
|
|
|
|
|
|
|
|
asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
|
|
|
|
: [ctl] "=r" (ctl));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return ctl;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Auxiliary Control Register */
|
|
|
|
static inline void write_actlr(u32_t ctl)
|
|
|
|
{
|
2013-09-25 10:53:41 +02:00
|
|
|
//http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babjbjbb.html
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
|
|
|
|
: : [ctl] "r" (ctl));
|
|
|
|
|
|
|
|
isb();
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read Current Program Status Register */
|
|
|
|
static inline u32_t read_cpsr()
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
u32_t status;
|
|
|
|
|
|
|
|
asm volatile("mrs %[status], cpsr @ read CPSR"
|
|
|
|
: [status] "=r" (status));
|
2012-10-08 03:38:03 +02:00
|
|
|
|
2013-02-15 01:07:04 +01:00
|
|
|
return status;
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write Current Program Status Register */
|
|
|
|
static inline void write_cpsr(u32_t status)
|
|
|
|
{
|
2013-02-15 01:07:04 +01:00
|
|
|
asm volatile("msr cpsr_c, %[status] @ write CPSR"
|
|
|
|
: : [status] "r" (status));
|
2012-10-08 03:38:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* _ARM_CPUFUNC_H */
|