arm:caching add methods to flush the data and unified cache
Change-Id: Idb066dd01afbdbccd684bcdcf4af88b4b1ef870a
This commit is contained in:
Kees Jongenburger
parent
c4ffaa0afb
commit
827378c57f
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@ -42,6 +42,123 @@ static inline void barrier(void)
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isb();
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}
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/* Read CLIDR, Cache Level ID Register */
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static inline u32_t read_clidr(){
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u32_t clidr;
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asm volatile("mrc p15, 1, %[clidr], c0, c0 , 1 @ READ CLIDR\n\t"
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: [clidr] "=r" (clidr));
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return clidr;
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}
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/* Read CSSELR, Cache Size Selection Register */
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static inline u32_t read_csselr(){
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u32_t csselr;
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asm volatile("mrc p15, 2, %[csselr], c0, c0 , 0 @ READ CSSELR\n\t"
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: [csselr] "=r" (csselr));
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return csselr;
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}
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/* Write CSSELR, Cache Size Selection Register */
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static inline void write_csselr(u32_t csselr){
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asm volatile("mcr p15, 2, %[csselr], c0, c0 , 0 @ WRITE CSSELR\n\t"
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: : [csselr] "r" (csselr));
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}
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/* Read Cache Size ID Register */
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static inline u32_t read_ccsidr()
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{
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u32_t ccsidr;
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asm volatile("mrc p15, 1, %[ccsidr], c0, c0, 0 @ Read CCSIDR\n\t"
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: [ccsidr] "=r" (ccsidr));
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return ccsidr;
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}
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/* Read TLBTR, TLB Type Register */
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static inline u32_t read_tlbtr()
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{
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u32_t tlbtr;
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asm volatile("mrc p15, 0, %[tlbtr], c0, c0, 3 @ Read TLBTR\n\t"
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: [tlbtr] "=r" (tlbtr));
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return tlbtr;
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}
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/* keesj:move these out */
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static inline u32_t ilog2(u32_t t)
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{
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u32_t counter =0;
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while( (t = t >> 1) ) counter ++;
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return counter;
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}
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/* keesj:move these out */
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static inline u32_t ipow2(u32_t t)
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{
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return 1 << t;
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}
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/*
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* type = 1 == CLEAN
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* type = 2 == INVALIDATE
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*/
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static inline void dcache_maint(int type){
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u32_t cache_level ;
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u32_t clidr;
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u32_t ctype;
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u32_t ccsidr;
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u32_t line_size,line_length;
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u32_t number_of_sets,number_of_ways;
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u32_t set,way;
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clidr = read_clidr();
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u32_t loc = ( clidr >> 24) & 0x7;
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u32_t louu = ( clidr >> 27) & 0x7;
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u32_t louis = ( clidr >> 21) & 0x7;
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for (cache_level =0 ; cache_level < loc; cache_level++){
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/* get current cache type */
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ctype = ( clidr >> cache_level*3) & 0x7;
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/* select data or unified or cache level */
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write_csselr(cache_level << 1);
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isb();
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ccsidr = read_ccsidr();
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line_size = ccsidr & 0x7;
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line_length = 2 << (line_size + 1) ; /* 2**(line_size + 2) */
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number_of_sets = ((ccsidr >> 13) & 0x7fff) + 1;
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number_of_ways = ((ccsidr >> 3) & 0x3ff) + 1;
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u32_t way_bits = ilog2(number_of_ways);
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if(ipow2(ilog2(number_of_ways) < number_of_ways) ) {
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way_bits++;
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}
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u32_t l = ilog2(line_length);
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for (way =0 ; way < number_of_ways; way++) {
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for (set =0 ; set < number_of_sets; set++) {
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u32_t val = ( way << (32 - way_bits) ) | (set << l) | (cache_level << 1 );
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if (type == 1) {
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/* DCCISW, Data Cache Clean and Invalidate by Set/Way */
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asm volatile("mcr p15, 0, %[set], c7, c14, 2 @ DCCISW"
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: : [set] "r" (val));
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} else if (type ==2 ){
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/* DCISW, Data Cache Invalidate by Set/Way */
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asm volatile("mcr p15, 0, %[set], c7, c6, 2"
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: : [set] "r" (val));
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}
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}
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}
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}
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dsb();
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isb();
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}
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static inline void dcache_clean(){
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dcache_maint(1);
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}
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static inline void dcache_invalidate (){
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dcache_maint(2);
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}
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static inline void refresh_tlb(void)
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{
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dsb();
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@ -57,7 +174,6 @@ static inline void refresh_tlb(void)
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asm volatile("mcr p15, 0, %[zero], c8, c5, 0" : : [zero] "r" (0));
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#endif
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#if 0
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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@ -66,7 +182,6 @@ static inline void refresh_tlb(void)
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/* Invalidate entire branch predictor array */
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asm volatile("mcr p15, 0, %[zero], c7, c5, 6" : : [zero] "r" (0)); /* flush BTB */
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#endif
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dsb();
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isb();
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@ -118,7 +233,6 @@ static inline void write_ttbr0(u32_t bar)
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static inline void reload_ttbr0(void)
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{
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reg_t ttbr = read_ttbr0();
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write_ttbr0(ttbr);
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}
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@ -317,6 +431,7 @@ static inline u32_t read_actlr()
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/* Write Auxiliary Control Register */
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static inline void write_actlr(u32_t ctl)
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{
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//http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babjbjbb.html
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
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: : [ctl] "r" (ctl));
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