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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.841612 # Number of seconds simulated
sim_ticks 1841612450000 # Number of ticks simulated
final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 222430 # Simulator instruction rate (inst/s)
host_op_rate 222430 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6273480939 # Simulator tick rate (ticks/s)
host_mem_usage 370816 # Number of bytes of host memory used
host_seconds 293.56 # Real time elapsed on the host
sim_insts 65295558 # Number of instructions simulated
sim_ops 65295558 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 476096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20002240 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2248832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 298304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2641344 # Number of bytes read from this memory
system.physmem.bytes_read::total 25814784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 476096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 298304 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 921408 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4825792 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
system.physmem.bytes_written::total 7485120 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7439 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 312535 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 35138 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4661 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 41271 # Number of read requests responded to by this memory
system.physmem.num_reads::total 403356 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 75403 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116955 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 258521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10861265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1221121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 161980 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1434256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14017490 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 258521 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 161980 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 500327 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2620417 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4064438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2620417 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 258521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10861265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1221121 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 161980 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1434256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18081928 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 83382 # Number of read requests accepted
system.physmem.writeReqs 46694 # Number of write requests accepted
system.physmem.readBursts 83382 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 46694 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5333696 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue
system.physmem.bytesWritten 2986816 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5336448 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 2988416 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 55 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5371 # Per bank write bursts
system.physmem.perBankRdBursts::1 5100 # Per bank write bursts
system.physmem.perBankRdBursts::2 5085 # Per bank write bursts
system.physmem.perBankRdBursts::3 5221 # Per bank write bursts
system.physmem.perBankRdBursts::4 5159 # Per bank write bursts
system.physmem.perBankRdBursts::5 5196 # Per bank write bursts
system.physmem.perBankRdBursts::6 5274 # Per bank write bursts
system.physmem.perBankRdBursts::7 5273 # Per bank write bursts
system.physmem.perBankRdBursts::8 5416 # Per bank write bursts
system.physmem.perBankRdBursts::9 5013 # Per bank write bursts
system.physmem.perBankRdBursts::10 5453 # Per bank write bursts
system.physmem.perBankRdBursts::11 5267 # Per bank write bursts
system.physmem.perBankRdBursts::12 4696 # Per bank write bursts
system.physmem.perBankRdBursts::13 5103 # Per bank write bursts
system.physmem.perBankRdBursts::14 5623 # Per bank write bursts
system.physmem.perBankRdBursts::15 5089 # Per bank write bursts
system.physmem.perBankWrBursts::0 2944 # Per bank write bursts
system.physmem.perBankWrBursts::1 2803 # Per bank write bursts
system.physmem.perBankWrBursts::2 2831 # Per bank write bursts
system.physmem.perBankWrBursts::3 3111 # Per bank write bursts
system.physmem.perBankWrBursts::4 3010 # Per bank write bursts
system.physmem.perBankWrBursts::5 2812 # Per bank write bursts
system.physmem.perBankWrBursts::6 3230 # Per bank write bursts
system.physmem.perBankWrBursts::7 2824 # Per bank write bursts
system.physmem.perBankWrBursts::8 3325 # Per bank write bursts
system.physmem.perBankWrBursts::9 2680 # Per bank write bursts
system.physmem.perBankWrBursts::10 3123 # Per bank write bursts
system.physmem.perBankWrBursts::11 2945 # Per bank write bursts
system.physmem.perBankWrBursts::12 2356 # Per bank write bursts
system.physmem.perBankWrBursts::13 2727 # Per bank write bursts
system.physmem.perBankWrBursts::14 3249 # Per bank write bursts
system.physmem.perBankWrBursts::15 2699 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 1840600173500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 83382 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 46694 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 66361 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7690 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 7479 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1778 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 743 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2799 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3540 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 3463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 2882 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 2796 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 2296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 2125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 21619 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 384.870346 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 218.868855 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 380.663334 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7130 32.98% 32.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 4830 22.34% 55.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 1852 8.57% 63.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1050 4.86% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 916 4.24% 72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 498 2.30% 75.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 396 1.83% 77.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 403 1.86% 78.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4544 21.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 21619 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 2039 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 40.867092 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 1027.907354 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 2037 99.90% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 2039 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 2039 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.888180 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.579378 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 22.470267 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 42 2.06% 2.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15 4 0.20% 2.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 1722 84.45% 86.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 114 5.59% 92.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 19 0.93% 93.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 3 0.15% 93.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 5 0.25% 93.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 2 0.10% 93.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 2 0.10% 93.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 3 0.15% 93.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 15 0.74% 94.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 5 0.25% 94.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 79 3.87% 98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 5 0.25% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 1 0.05% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 5 0.25% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 5 0.25% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 3 0.15% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 1 0.05% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 1 0.05% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.10% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 2039 # Writes before turning the bus around for reads
system.physmem.totQLat 882163500 # Total ticks spent queuing
system.physmem.totMemAccLat 2444769750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 416695000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10585.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29335.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgWrQLen 8.38 # Average write queue length when enqueuing
system.physmem.readRowHits 71513 # Number of row buffer hits during reads
system.physmem.writeRowHits 36876 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.97 # Row buffer hit rate for writes
system.physmem.avgGap 14150190.45 # Average gap between requests
system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1766563042250 # Time in different power states
system.physmem.memoryStateTime::REF 61495460000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.trans_dist::ReadReq 294949 # Transaction distribution
system.membus.trans_dist::ReadResp 294942 # Transaction distribution
system.membus.trans_dist::WriteReq 9810 # Transaction distribution
system.membus.trans_dist::WriteResp 9810 # Transaction distribution
system.membus.trans_dist::Writeback 75403 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 148 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 150 # Transaction distribution
system.membus.trans_dist::ReadExReq 115716 # Transaction distribution
system.membus.trans_dist::ReadExResp 115716 # Transaction distribution
system.membus.trans_dist::BadAddressError 7 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882385 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 916307 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83395 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83395 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 999702 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30639616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 30685184 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2666880 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2666880 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33352064 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 55 # Total snoops (count)
system.membus.snoop_fanout::samples 520629 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 520629 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 520629 # Request fanout histogram
system.membus.reqLayer0.occupancy 11839500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 516853000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 782820695 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 17912499 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 337573 # number of replacements
system.l2c.tags.tagsinuse 65418.651212 # Cycle average of tags in use
system.l2c.tags.total_refs 2486411 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402735 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.173814 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54701.898581 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2338.827583 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2722.708612 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 571.952854 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 605.884854 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2274.772027 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2202.606700 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.834685 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.035688 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.041545 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.008727 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009245 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.034710 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998209 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55337 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 26257052 # Number of tag accesses
system.l2c.tags.data_accesses 26257052 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 505398 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 481784 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 121841 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 80801 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 322748 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 255127 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1767699 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835833 # number of Writeback hits
system.l2c.Writeback_hits::total 835833 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 90729 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 25227 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 70911 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186867 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 505398 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 572513 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 121841 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 106028 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 322748 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 326038 # number of demand (read+write) hits
system.l2c.demand_hits::total 1954566 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 505398 # number of overall hits
system.l2c.overall_hits::cpu0.data 572513 # number of overall hits
system.l2c.overall_hits::cpu1.inst 121841 # number of overall hits
system.l2c.overall_hits::cpu1.data 106028 # number of overall hits
system.l2c.overall_hits::cpu2.inst 322748 # number of overall hits
system.l2c.overall_hits::cpu2.data 326038 # number of overall hits
system.l2c.overall_hits::total 1954566 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7439 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 238433 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2297 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 16797 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 4661 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 18005 # number of ReadReq misses
system.l2c.ReadReq_misses::total 287632 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 24 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 74189 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 18351 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 23300 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115840 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 7439 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 312622 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 35148 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4661 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 41305 # number of demand (read+write) misses
system.l2c.demand_misses::total 403472 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7439 # number of overall misses
system.l2c.overall_misses::cpu0.data 312622 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses
system.l2c.overall_misses::cpu1.data 35148 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4661 # number of overall misses
system.l2c.overall_misses::cpu2.data 41305 # number of overall misses
system.l2c.overall_misses::total 403472 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 172213000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1123783250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 353640000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1207129000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2856765250 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 175993 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 175993 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 46498 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1259346740 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1952437723 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3211784463 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 172213000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2383129990 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 353640000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3159566723 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6068549713 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 172213000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2383129990 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 353640000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3159566723 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6068549713 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 512837 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 720217 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 124138 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 97598 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 327409 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 273132 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2055331 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835833 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835833 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 26 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 8 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 164918 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 43578 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 94211 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302707 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 512837 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 885135 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 124138 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 141176 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 327409 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 367343 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2358038 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 512837 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 885135 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 124138 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 141176 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 327409 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 367343 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2358038 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014506 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.331057 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.018504 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.172104 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014236 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.065921 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.139944 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.615385 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.631579 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.449854 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.421107 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.247317 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382680 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014506 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.353191 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.018504 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.248966 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014236 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.112443 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.171105 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014506 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.353191 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.018504 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.248966 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014236 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.112443 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.171105 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74973.008272 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 66903.807227 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75872.130444 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 67044.098861 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 9932.014692 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10999.562500 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 7333.041667 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 23249 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68625.510326 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83795.610429 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 27726.039908 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74973.008272 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 67802.719643 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 75872.130444 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 76493.565501 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 15040.819965 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74973.008272 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 67802.719643 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 75872.130444 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 76493.565501 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 15040.819965 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 75403 # number of writebacks
system.l2c.writebacks::total 75403 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 16797 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 4661 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 18005 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 41760 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 18351 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 23300 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 41651 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 35148 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4661 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 41305 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 83411 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 35148 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4661 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 41305 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 83411 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 142970000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 913492250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 294969000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 982528500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2333959750 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 173016 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 173016 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20002 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1028775260 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1667747777 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2696523037 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 142970000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1942267510 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 294969000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2650276277 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5030482787 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 142970000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1942267510 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 294969000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2650276277 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5030482787 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 233807000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320899000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 554706000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302174000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 396022500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 698196500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535981000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716921500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1252902500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172104 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.065921 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020318 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.615385 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.421053 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421107 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.247317 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.137595 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.248966 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.112443 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.035373 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018504 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.248966 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014236 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.112443 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.035373 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54384.250164 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54569.758400 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55889.840757 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10813.500000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10813.500000 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56060.991772 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71577.157811 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64740.895465 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254811 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1693889963000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254811 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078426 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078426 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 41552 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039517841 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039517841 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60157.282465 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60157.282465 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4820532 # DTB read hits
system.cpu0.dtb.read_misses 5970 # DTB read misses
system.cpu0.dtb.read_acv 109 # DTB read access violations
system.cpu0.dtb.read_accesses 427970 # DTB read accesses
system.cpu0.dtb.write_hits 3430087 # DTB write hits
system.cpu0.dtb.write_misses 674 # DTB write misses
system.cpu0.dtb.write_acv 81 # DTB write access violations
system.cpu0.dtb.write_accesses 164325 # DTB write accesses
system.cpu0.dtb.data_hits 8250619 # DTB hits
system.cpu0.dtb.data_misses 6644 # DTB misses
system.cpu0.dtb.data_acv 190 # DTB access violations
system.cpu0.dtb.data_accesses 592295 # DTB accesses
system.cpu0.itb.fetch_hits 2728150 # ITB hits
system.cpu0.itb.fetch_misses 3015 # ITB misses
system.cpu0.itb.fetch_acv 97 # ITB acv
system.cpu0.itb.fetch_accesses 2731165 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 929887646 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 30964546 # Number of instructions committed
system.cpu0.committedOps 30964546 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 28877269 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 164895 # Number of float alu accesses
system.cpu0.num_func_calls 798898 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3870413 # number of instructions that are conditional controls
system.cpu0.num_int_insts 28877269 # number of integer instructions
system.cpu0.num_fp_insts 164895 # number of float instructions
system.cpu0.num_int_register_reads 39993375 # number of times the integer registers were read
system.cpu0.num_int_register_writes 21214284 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 85263 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 86719 # number of times the floating registers were written
system.cpu0.num_mem_refs 8280000 # number of memory refs
system.cpu0.num_load_insts 4841351 # Number of load instructions
system.cpu0.num_store_insts 3438649 # Number of store instructions
system.cpu0.num_idle_cycles 908004121.642144 # Number of idle cycles
system.cpu0.num_busy_cycles 21883524.357856 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023534 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976466 # Percentage of idle cycles
system.cpu0.Branches 4926659 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1578204 5.10% 5.10% # Class of executed instruction
system.cpu0.op_class::IntAlu 20416117 65.92% 71.01% # Class of executed instruction
system.cpu0.op_class::IntMult 31858 0.10% 71.12% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
system.cpu0.op_class::FloatAdd 12902 0.04% 71.16% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1598 0.01% 71.16% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.16% # Class of executed instruction
system.cpu0.op_class::MemRead 4972343 16.05% 87.22% # Class of executed instruction
system.cpu0.op_class::MemWrite 3441751 11.11% 98.33% # Class of executed instruction
system.cpu0.op_class::IprAccess 516607 1.67% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 30971380 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211354 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182556 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1818780188000 98.76% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 39182000 0.00% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 357649000 0.02% 98.78% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22434661500 1.22% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1841611680500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815832 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175299 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192210 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1907
system.cpu0.kern.mode_good::user 1738
system.cpu0.kern.mode_good::idle 169
system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29705567000 1.61% 1.61% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2577814500 0.14% 1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1809328294500 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 2062606 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2062584 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 835833 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 17283 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 38 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 46 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 302707 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 302707 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 7 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1928849 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657196 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5586045 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61721856 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142735808 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 204457664 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 41925 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3235706 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.012896 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.112826 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3193978 98.71% 98.71% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 41728 1.29% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3235706 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2218971499 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2034366165 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2306919756 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
system.iobus.trans_dist::WriteResp 27090 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 24272 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 2079000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 9370000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17534501 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 963743 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.196442 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 40274426 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 964254 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 41.767445 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.296847 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.404531 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.495065 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.514252 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131649 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.352529 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998431 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 42219519 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42219519 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 30458523 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7341413 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2474490 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 40274426 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30458523 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7341413 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2474490 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 40274426 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30458523 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7341413 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2474490 # number of overall hits
system.cpu0.icache.overall_hits::total 40274426 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 512857 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 124138 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 343653 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 980648 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 512857 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 124138 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 343653 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 980648 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 512857 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 124138 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 343653 # number of overall misses
system.cpu0.icache.overall_misses::total 980648 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1770888500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4833799298 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6604687798 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1770888500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4833799298 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6604687798 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1770888500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4833799298 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6604687798 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30971380 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7465551 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2818143 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 41255074 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30971380 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7465551 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2818143 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 41255074 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30971380 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7465551 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2818143 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 41255074 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016559 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016628 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121943 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.023770 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016559 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016628 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121943 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.023770 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016559 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016628 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121943 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.023770 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.482769 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14065.930744 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6735.023982 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6735.023982 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6735.023982 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.645963 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16203 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16203 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16203 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16203 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16203 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16203 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124138 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327450 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 451588 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 124138 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 327450 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 451588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 124138 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 327450 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 451588 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1521699500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997566325 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5519265825 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1521699500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997566325 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5519265825 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1521699500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997566325 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5519265825 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010946 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.010946 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.010946 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.905420 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1393134 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13262946 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1393646 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.516725 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.690760 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.796063 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.510993 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.511115 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146086 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.342795 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63351559 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63351559 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 3996259 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1054031 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2516397 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7566687 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3140432 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 808252 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1363715 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5312399 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114574 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18764 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51112 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184450 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123404 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20737 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55180 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199321 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7136691 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1862283 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 3880112 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12879086 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7136691 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1862283 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3880112 # number of overall hits
system.cpu0.dcache.overall_hits::total 12879086 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 710837 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 95497 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 564447 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1370781 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 164929 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 43579 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 628162 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 836670 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9380 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2101 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7681 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 19162 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 8 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 875766 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 139076 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1192609 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2207451 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 875766 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 139076 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1192609 # number of overall misses
system.cpu0.dcache.overall_misses::total 2207451 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2207514000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9811838599 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 12019352599 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1651311760 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20363561979 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 22014873739 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27705250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 128352996 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 156058246 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 130502 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 130502 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 3858825760 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 30175400578 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 34034226338 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 3858825760 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 30175400578 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 34034226338 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4707096 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1149528 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 3080844 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8937468 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3305361 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 851831 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1991877 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6149069 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123954 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20865 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58793 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203612 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123404 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20737 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55188 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199329 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8012457 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2001359 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 5072721 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15086537 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8012457 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2001359 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 5072721 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15086537 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151014 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083075 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183212 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.153375 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049897 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051159 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315362 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.136065 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075673 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100695 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130645 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094110 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000145 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109301 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069491 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235102 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.146319 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109301 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069491 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235102 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.146319 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23116.056002 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17383.099917 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8768.251529 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37892.373850 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32417.691581 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 26312.493264 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13186.696811 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16710.453847 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8144.152281 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16312.750000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16312.750000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27746.165837 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.006423 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15417.885307 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27746.165837 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25302.006423 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15417.885307 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 891586 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 724 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 62691 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.221914 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 80.444444 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835833 # number of writebacks
system.cpu0.dcache.writebacks::total 835833 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 297087 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 297087 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534212 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 534212 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1624 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1624 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 831299 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 831299 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 831299 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 831299 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95497 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267360 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 362857 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43579 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 93950 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 137529 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2101 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6057 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8158 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 139076 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 361310 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 500386 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 139076 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 361310 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 500386 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2008989000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4477810640 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6486799640 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555821240 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2924918842 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4480740082 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23501750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 73479753 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96981503 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 114498 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 114498 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3564810240 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7402729482 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10967539722 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3564810240 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7402729482 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10967539722 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249745500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342957000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592702500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320247000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420262500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740509500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569992500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 763219500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333212000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083075 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086781 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040600 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051159 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047167 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022366 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100695 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103022 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040066 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000145 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033168 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033168 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1168269 # DTB read hits
system.cpu1.dtb.read_misses 1330 # DTB read misses
system.cpu1.dtb.read_acv 35 # DTB read access violations
system.cpu1.dtb.read_accesses 141659 # DTB read accesses
system.cpu1.dtb.write_hits 872893 # DTB write hits
system.cpu1.dtb.write_misses 171 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 57101 # DTB write accesses
system.cpu1.dtb.data_hits 2041162 # DTB hits
system.cpu1.dtb.data_misses 1501 # DTB misses
system.cpu1.dtb.data_acv 57 # DTB access violations
system.cpu1.dtb.data_accesses 198760 # DTB accesses
system.cpu1.itb.fetch_hits 849127 # ITB hits
system.cpu1.itb.fetch_misses 665 # ITB misses
system.cpu1.itb.fetch_acv 34 # ITB acv
system.cpu1.itb.fetch_accesses 849792 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953403050 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7463992 # Number of instructions committed
system.cpu1.committedOps 7463992 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 6937939 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 43895 # Number of float alu accesses
system.cpu1.num_func_calls 203449 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 905325 # number of instructions that are conditional controls
system.cpu1.num_int_insts 6937939 # number of integer instructions
system.cpu1.num_fp_insts 43895 # number of float instructions
system.cpu1.num_int_register_reads 9652072 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5060714 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 23736 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24066 # number of times the floating registers were written
system.cpu1.num_mem_refs 2048141 # number of memory refs
system.cpu1.num_load_insts 1172984 # Number of load instructions
system.cpu1.num_store_insts 875157 # Number of store instructions
system.cpu1.num_idle_cycles 923975246.943285 # Number of idle cycles
system.cpu1.num_busy_cycles 29427803.056715 # Number of busy cycles
system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles
system.cpu1.Branches 1173357 # Number of branches fetched
system.cpu1.op_class::No_OpClass 399705 5.35% 5.35% # Class of executed instruction
system.cpu1.op_class::IntAlu 4844088 64.89% 70.24% # Class of executed instruction
system.cpu1.op_class::IntMult 8214 0.11% 70.35% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction
system.cpu1.op_class::FloatAdd 5110 0.07% 70.42% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction
system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction
system.cpu1.op_class::MemRead 1201071 16.09% 86.52% # Class of executed instruction
system.cpu1.op_class::MemWrite 876369 11.74% 98.26% # Class of executed instruction
system.cpu1.op_class::IprAccess 130183 1.74% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 7465550 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 9020137 # Number of BP lookups
system.cpu2.branchPred.condPredicted 8282573 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 6965204 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 4892106 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 70.236364 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 299658 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 7807 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3485260 # DTB read hits
system.cpu2.dtb.read_misses 12402 # DTB read misses
system.cpu2.dtb.read_acv 152 # DTB read access violations
system.cpu2.dtb.read_accesses 227268 # DTB read accesses
system.cpu2.dtb.write_hits 2138350 # DTB write hits
system.cpu2.dtb.write_misses 2805 # DTB write misses
system.cpu2.dtb.write_acv 140 # DTB write access violations
system.cpu2.dtb.write_accesses 85115 # DTB write accesses
system.cpu2.dtb.data_hits 5623610 # DTB hits
system.cpu2.dtb.data_misses 15207 # DTB misses
system.cpu2.dtb.data_acv 292 # DTB access violations
system.cpu2.dtb.data_accesses 312383 # DTB accesses
system.cpu2.itb.fetch_hits 538601 # ITB hits
system.cpu2.itb.fetch_misses 5813 # ITB misses
system.cpu2.itb.fetch_acv 166 # ITB acv
system.cpu2.itb.fetch_accesses 544414 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 29513686 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9389582 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 35469274 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 9020137 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 5191764 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 18021119 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 410530 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 647 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 9356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 228650 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 98931 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 387 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2818143 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 92772 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 27955647 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.268770 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.388372 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 20239272 72.40% 72.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 311789 1.12% 73.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 473018 1.69% 75.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3278988 11.73% 86.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 836372 2.99% 89.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 194449 0.70% 90.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 239819 0.86% 91.48% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 437682 1.57% 93.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1944258 6.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 27955647 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.305626 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.201791 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 7697914 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 13194592 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 6089531 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 535341 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 192357 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 175638 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 13257 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 32098439 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 42458 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 192357 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 7981444 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 4806689 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 6360452 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 6310892 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 2057913 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 31276153 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 68586 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 406035 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 57262 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 980638 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 20937225 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 38641604 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 38581458 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 56230 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 19023888 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1913337 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 532654 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 63537 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3939185 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3509523 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2229292 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 463055 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 331167 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 28745476 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 680921 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 28394222 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 16375 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2445259 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1154216 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 487025 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 27955647 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.015688 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.594887 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 17573743 62.86% 62.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 2782129 9.95% 72.81% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1379697 4.94% 77.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 4038946 14.45% 92.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 1015784 3.63% 95.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 573145 2.05% 97.88% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 387606 1.39% 99.27% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 155412 0.56% 99.82% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 49185 0.18% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 27955647 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 83781 21.60% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 179225 46.21% 67.82% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 124810 32.18% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 22268545 78.43% 78.43% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 21109 0.07% 78.51% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.51% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 20518 0.07% 78.58% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.58% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.58% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.58% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.59% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3613635 12.73% 91.31% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2162330 7.62% 98.93% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 304401 1.07% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 28394222 # Type of FU issued
system.cpu2.iq.rate 0.962070 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 387816 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.013658 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 84894498 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 31757890 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 27813110 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 253784 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 119651 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 117192 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 28643478 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 136104 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 207211 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 438819 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1413 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 6020 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 178766 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5023 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 176307 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 192357 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 4003600 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 328635 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 30811270 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 51966 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3509523 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2229292 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 606230 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 15640 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 265026 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 6020 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 63511 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 134698 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 198209 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 28196871 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3506429 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 197351 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1384873 # number of nop insts executed
system.cpu2.iew.exec_refs 5652310 # number of memory reference insts executed
system.cpu2.iew.exec_branches 5956275 # Number of branches executed
system.cpu2.iew.exec_stores 2145881 # Number of stores executed
system.cpu2.iew.exec_rate 0.955383 # Inst execution rate
system.cpu2.iew.wb_sent 27971955 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 27930302 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 15891558 # num instructions producing a value
system.cpu2.iew.wb_consumers 19546280 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.946351 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.813022 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2680068 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 193896 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 181086 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 27486207 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.021790 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.858200 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 18368842 66.83% 66.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2248676 8.18% 75.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1182960 4.30% 79.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 3745017 13.63% 92.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 544035 1.98% 94.92% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 201250 0.73% 95.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 165260 0.60% 96.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 179807 0.65% 96.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 850360 3.09% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 27486207 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 28085126 # Number of instructions committed
system.cpu2.commit.committedOps 28085126 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 5121230 # Number of memory references committed
system.cpu2.commit.loads 3070704 # Number of loads committed
system.cpu2.commit.membars 68250 # Number of memory barriers committed
system.cpu2.commit.branches 5783973 # Number of branches committed
system.cpu2.commit.fp_insts 115466 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 26570607 # Number of committed integer instructions.
system.cpu2.commit.function_calls 240322 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 1220562 4.35% 4.35% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 21327099 75.94% 80.28% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.36% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.36% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 20069 0.07% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 3138954 11.18% 91.61% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 2052162 7.31% 98.92% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 304401 1.08% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 28085126 # Class of committed instruction
system.cpu2.commit.bw_lim_events 850360 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 57323983 # The number of ROB reads
system.cpu2.rob.rob_writes 61998256 # The number of ROB writes
system.cpu2.timesIdled 175445 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1558039 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1746293269 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 26867020 # Number of Instructions Simulated
system.cpu2.committedOps 26867020 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.098510 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.098510 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.910324 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.910324 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 36957336 # number of integer regfile reads
system.cpu2.int_regfile_writes 19827241 # number of integer regfile writes
system.cpu2.fp_regfile_reads 70923 # number of floating regfile reads
system.cpu2.fp_regfile_writes 71075 # number of floating regfile writes
system.cpu2.misc_regfile_reads 3638892 # number of misc regfile reads
system.cpu2.misc_regfile_writes 273174 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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