gem5/src/arch/x86/isa
Gabe Black aaa30714b3 X86: Various fixes to indexing segmentation related registers
--HG--
extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
2007-11-12 14:37:54 -08:00
..
decoder X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions. 2007-10-19 15:21:16 -07:00
formats X86: Make the "fault" microop predicated. 2007-10-18 22:40:18 -07:00
insts X86: Use the cda microop where appropriate. The ENTER instruction still needs these. 2007-10-22 14:39:40 -07:00
microops X86: Various fixes to indexing segmentation related registers 2007-11-12 14:37:54 -08:00
bitfields.isa X86: Add a bitfield to indicate whether or not an REX prefix was present. 2007-07-30 13:17:34 -07:00
includes.isa X86: Implement the ldst microop and put it in existing microcode where appropriate. 2007-10-02 22:08:09 -07:00
macroop.isa X86: Implement the in/out instructions. These will still need support from the TLB and memory system. 2007-10-18 22:39:00 -07:00
main.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
microasm.isa X86: Various fixes to indexing segmentation related registers 2007-11-12 14:37:54 -08:00
operands.isa X86: Move the fp microops to their own file with their own base classes in C++ and python. 2007-09-19 18:27:55 -07:00
outputblock.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
specialize.isa X86: Added some new versions of MOV and a new argument type tag. 2007-10-12 20:08:12 -07:00