2554 lines
295 KiB
Text
2554 lines
295 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.104766 # Number of seconds simulated
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sim_ticks 1104766159000 # Number of ticks simulated
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final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 49697 # Simulator instruction rate (inst/s)
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host_op_rate 63978 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 891289209 # Simulator tick rate (ticks/s)
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host_mem_usage 450492 # Number of bytes of host memory used
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host_seconds 1239.51 # Real time elapsed on the host
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sim_insts 61600257 # Number of instructions simulated
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sim_ops 79301805 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory
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system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 6257980 # Number of read requests accepted
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system.physmem.writeReqs 823516 # Number of write requests accepted
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system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 391105 # Per bank write bursts
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system.physmem.perBankRdBursts::1 391040 # Per bank write bursts
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system.physmem.perBankRdBursts::2 387008 # Per bank write bursts
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system.physmem.perBankRdBursts::3 386856 # Per bank write bursts
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system.physmem.perBankRdBursts::4 391768 # Per bank write bursts
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system.physmem.perBankRdBursts::5 391357 # Per bank write bursts
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system.physmem.perBankRdBursts::6 387221 # Per bank write bursts
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system.physmem.perBankRdBursts::7 386642 # Per bank write bursts
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system.physmem.perBankRdBursts::8 391438 # Per bank write bursts
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system.physmem.perBankRdBursts::9 391160 # Per bank write bursts
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system.physmem.perBankRdBursts::10 385906 # Per bank write bursts
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system.physmem.perBankRdBursts::11 385319 # Per bank write bursts
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system.physmem.perBankRdBursts::12 390977 # Per bank write bursts
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system.physmem.perBankRdBursts::13 390642 # Per bank write bursts
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system.physmem.perBankRdBursts::14 386557 # Per bank write bursts
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system.physmem.perBankRdBursts::15 386235 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7173 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7194 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7298 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7217 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7815 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7451 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7359 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7185 # Per bank write bursts
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|
system.physmem.perBankWrBursts::8 7499 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7507 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6838 # Per bank write bursts
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|
system.physmem.perBankWrBursts::11 6616 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7156 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6834 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7291 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7179 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 1104765054500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 105 # Read request sizes (log2)
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system.physmem.readPktSize::3 6094848 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 163027 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 756836 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66680 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1159 139 0.20% 77.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1223 90 0.13% 77.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1287 153 0.22% 77.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1351 51 0.07% 77.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1415 550 0.78% 78.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1479 38 0.05% 78.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1543 222 0.31% 78.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1607 29 0.04% 78.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1671 108 0.15% 78.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1735 16 0.02% 78.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1927 57 0.08% 79.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1991 19 0.03% 79.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2055 237 0.33% 79.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2119 12 0.02% 79.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2183 45 0.06% 79.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2247 10 0.01% 79.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2311 54 0.08% 79.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2375 16 0.02% 79.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2439 29 0.04% 79.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2503 2 0.00% 79.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2567 27 0.04% 79.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2631 2 0.00% 79.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2695 17 0.02% 79.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2759 5 0.01% 79.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2823 28 0.04% 79.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2887 7 0.01% 79.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2951 22 0.03% 80.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3079 178 0.25% 80.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4615 19 0.03% 81.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4743 6 0.01% 81.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4871 20 0.03% 81.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4999 13 0.02% 81.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5063 3 0.00% 81.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6535 12 0.02% 82.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6599 4 0.01% 82.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6663 80 0.11% 82.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6727 5 0.01% 82.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6791 21 0.03% 82.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6855 6 0.01% 82.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6919 25 0.04% 82.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7047 3 0.00% 82.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7111 5 0.01% 82.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7175 24 0.03% 82.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7303 4 0.01% 82.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7367 11 0.02% 82.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7431 94 0.13% 82.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10247 80 0.11% 83.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10503 87 0.12% 84.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10560-10567 1 0.00% 84.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10624-10631 2 0.00% 84.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10688-10695 1 0.00% 84.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10759 16 0.02% 84.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11015 75 0.11% 84.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11271 80 0.11% 84.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11328-11335 2 0.00% 84.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11783 10 0.01% 84.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12039 70 0.10% 84.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12295 175 0.25% 84.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12551 22 0.03% 84.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12807 37 0.05% 84.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13063 80 0.11% 84.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13319 161 0.23% 85.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13575 8 0.01% 85.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13831 12 0.02% 85.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13888-13895 2 0.00% 85.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13952-13959 2 0.00% 85.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14087 25 0.04% 85.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14144-14151 1 0.00% 85.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14208-14215 1 0.00% 85.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14343 180 0.25% 85.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14528-14535 1 0.00% 85.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14599 23 0.03% 85.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14855 2 0.00% 85.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15111 22 0.03% 85.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15367 213 0.30% 85.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15552-15559 1 0.00% 85.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15623 15 0.02% 85.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15680-15687 2 0.00% 85.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15879 5 0.01% 85.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15936-15943 1 0.00% 85.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16135 4 0.01% 85.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16199 3 0.00% 85.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16391 278 0.39% 86.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16647 6 0.01% 86.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16903 6 0.01% 86.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17159 16 0.02% 86.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17216-17223 2 0.00% 86.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17280-17287 4 0.01% 86.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17408-17415 216 0.30% 86.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17600-17607 4 0.01% 86.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17671 28 0.04% 86.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17927 6 0.01% 86.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18112-18119 2 0.00% 86.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18183 20 0.03% 86.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18439 175 0.25% 86.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18695 21 0.03% 86.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18752-18759 2 0.00% 86.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18944-18951 11 0.02% 86.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19207 12 0.02% 86.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19392-19399 2 0.00% 86.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19463 153 0.22% 87.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19648-19655 2 0.00% 87.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19719 76 0.11% 87.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19776-19783 4 0.01% 87.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19840-19847 1 0.00% 87.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-19975 33 0.05% 87.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20231 20 0.03% 87.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20487 171 0.24% 87.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20743 75 0.11% 87.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21248-21255 17 0.02% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21376-21383 3 0.00% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21511 73 0.10% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21568-21575 1 0.00% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21632-21639 1 0.00% 87.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21824-21831 2 0.00% 87.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21888-21895 1 0.00% 87.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22023 12 0.02% 88.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22080-22087 1 0.00% 88.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22144-22151 1 0.00% 88.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22208-22215 2 0.00% 88.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22279 88 0.12% 88.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22535 73 0.10% 88.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22656-22663 3 0.00% 88.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22784-22791 94 0.13% 88.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23047 67 0.09% 88.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23168-23175 1 0.00% 88.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23424-23431 1 0.00% 88.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23559 18 0.03% 88.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23680-23687 2 0.00% 88.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23744-23751 1 0.00% 88.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23815 82 0.12% 88.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24071 73 0.10% 88.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24320-24327 24 0.03% 88.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24583 150 0.21% 88.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24832-24839 25 0.04% 89.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24960-24967 1 0.00% 89.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25095 68 0.10% 89.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25351 86 0.12% 89.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25536-25543 1 0.00% 89.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25607 20 0.03% 89.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25856-25863 14 0.02% 89.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25984-25991 3 0.00% 89.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26048-26055 1 0.00% 89.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26119 69 0.10% 89.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26240-26247 2 0.00% 89.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26375 93 0.13% 89.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26631 75 0.11% 89.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26688-26695 1 0.00% 89.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26887 84 0.12% 89.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27072-27079 1 0.00% 89.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27136-27143 14 0.02% 89.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27328-27335 2 0.00% 89.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27399 75 0.11% 89.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27655 77 0.11% 90.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27712-27719 1 0.00% 90.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27840-27847 1 0.00% 90.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28032-28039 1 0.00% 90.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28096-28103 1 0.00% 90.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28160-28167 8 0.01% 90.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28288-28295 1 0.00% 90.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28423 75 0.11% 90.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28679 176 0.25% 90.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28935 20 0.03% 90.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28992-28999 1 0.00% 90.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29056-29063 2 0.00% 90.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29191 31 0.04% 90.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29248-29255 1 0.00% 90.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29312-29319 2 0.00% 90.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29376-29383 3 0.00% 90.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29447 76 0.11% 90.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29703 149 0.21% 90.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29824-29831 1 0.00% 90.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30215 7 0.01% 90.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30471 23 0.03% 90.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30727 175 0.25% 91.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30784-30791 2 0.00% 91.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30912-30919 6 0.01% 91.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30976-30983 19 0.03% 91.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31239 4 0.01% 91.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31495 24 0.03% 91.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31616-31623 2 0.00% 91.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31680-31687 1 0.00% 91.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31751 210 0.30% 91.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32263 5 0.01% 91.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32519 5 0.01% 91.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32704-32711 2 0.00% 91.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32775 275 0.39% 91.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33031 4 0.01% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33287 5 0.01% 91.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33408-33415 1 0.00% 91.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33536-33543 21 0.03% 92.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33799 214 0.30% 92.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34048-34055 20 0.03% 92.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34311 2 0.00% 92.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34560-34567 21 0.03% 92.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34823 167 0.24% 92.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35079 18 0.03% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35200-35207 1 0.00% 92.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35328-35335 7 0.01% 92.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35520-35527 1 0.00% 92.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35712-35719 1 0.00% 92.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35847 147 0.21% 92.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35968-35975 1 0.00% 92.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36096-36103 73 0.10% 92.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36160-36167 1 0.00% 92.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36352-36359 29 0.04% 93.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36416-36423 1 0.00% 93.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36608-36615 20 0.03% 93.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38656-38663 83 0.12% 93.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38912-38919 77 0.11% 93.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39040-39047 2 0.00% 93.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39168-39175 93 0.13% 94.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39360-39367 1 0.00% 94.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39431 65 0.09% 94.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39552-39559 1 0.00% 94.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39680-39687 10 0.01% 94.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39936-39943 17 0.02% 94.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40000-40007 2 0.00% 94.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation
|
|
system.physmem.totQLat 151784626000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.87 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 6167948 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 98004 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 156007.30 # Average gap between requests
|
|
system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 62368825 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 7306736 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 7306736 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 767886 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 767886 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66680 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 138080 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 137692 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 68902967 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
|
|
system.l2c.tags.replacements 72740 # number of replacements
|
|
system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 581363 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 140 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 48345 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 58632 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 106977 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 22002 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 4348 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 385872 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 214889 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 31083 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 5052 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 589425 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 256959 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 214889 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 256959 # number of overall hits
|
|
system.l2c.overall_hits::total 1509630 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 6278 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6388 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 6245 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 25248 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 5144 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3776 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 8920 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 420 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1053 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 63281 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 77008 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 6278 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 83253 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 165537 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 6278 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 69669 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 83253 # number of overall misses
|
|
system.l2c.overall_misses::total 165537 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1043750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 232500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 459739750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 479407748 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1279750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 475943000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 485330750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1902977248 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 8942096 # number of UpgradeReq miss cycles
|
|
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|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 5714736184 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 10521689078 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 881250 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 380499000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 4027956894 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 396299500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 5714736184 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 10521689078 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399518741 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603727234 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 167012025973 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1005734999 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16506425201 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 17512160200 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13405253740 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 136617428 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 146120255 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 46298079 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 7945 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 7945 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 51148551 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
system.cpu0.branchPred.lookups 5998612 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 8906772 # DTB read hits
|
|
system.cpu0.dtb.read_misses 28714 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5141355 # DTB write hits
|
|
system.cpu0.dtb.write_misses 5491 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 8935486 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5146846 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14048127 # DTB hits
|
|
system.cpu0.dtb.misses 34205 # DTB misses
|
|
system.cpu0.dtb.accesses 14082332 # DTB accesses
|
|
system.cpu0.itb.inst_hits 4217878 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 5102 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses
|
|
system.cpu0.itb.hits 4217878 # DTB hits
|
|
system.cpu0.itb.misses 5102 # DTB misses
|
|
system.cpu0.itb.accesses 4222980 # DTB accesses
|
|
system.cpu0.numCycles 69399845 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued
|
|
system.cpu0.iq.rate 0.536728 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 117147 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 4855012 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5401246 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.531281 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 18314277 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 23685352 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 11431143 # Number of memory references committed
|
|
system.cpu0.commit.loads 6279002 # Number of loads committed
|
|
system.cpu0.commit.membars 229688 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 4246153 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 489419 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 75718589 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 75736714 # The number of ROB writes
|
|
system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 23604610 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated
|
|
system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 904 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes
|
|
system.cpu0.icache.tags.replacements 392190 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 3792228 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 423961 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 276315 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139214 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 139214 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137082 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 137082 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 8940115 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 8940115 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 8940115 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 8940115 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 391237 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 391237 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1585894 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1585894 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8707 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 8707 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1977131 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1977131 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1977131 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1977131 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519617945 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5519617945 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79664471073 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 79664471073 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90084987 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 90084987 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45897132 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 45897132 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 85184089018 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 85184089018 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 85184089018 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 85184089018 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172471 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6172471 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744775 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4744775 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147921 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 147921 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144548 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 144548 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 10917246 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 10917246 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 10917246 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 10917246 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063384 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.063384 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334240 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.334240 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058863 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058863 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051651 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051651 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181102 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.181102 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 256502 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 8777296 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions.
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 42697243 # DTB read hits
|
|
system.cpu1.dtb.read_misses 36228 # DTB read misses
|
|
system.cpu1.dtb.write_hits 6821056 # DTB write hits
|
|
system.cpu1.dtb.write_misses 10680 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 42733471 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 6831736 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 49518299 # DTB hits
|
|
system.cpu1.dtb.misses 46908 # DTB misses
|
|
system.cpu1.dtb.accesses 49565207 # DTB accesses
|
|
system.cpu1.itb.inst_hits 7578630 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 5358 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses
|
|
system.cpu1.itb.hits 7578630 # DTB hits
|
|
system.cpu1.itb.misses 5358 # DTB misses
|
|
system.cpu1.itb.accesses 7583988 # DTB accesses
|
|
system.cpu1.numCycles 409868912 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued
|
|
system.cpu1.iq.rate 0.214000 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 104468 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 6912361 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 7107436 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.209797 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 29705560 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 38065286 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 16595591 # Number of memory references committed
|
|
system.cpu1.commit.loads 9755506 # Number of loads committed
|
|
system.cpu1.commit.membars 190120 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 5967745 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 534627 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 170668638 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 125130415 # The number of ROB writes
|
|
system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 37995647 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated
|
|
system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes
|
|
system.cpu1.icache.tags.replacements 595825 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 6935518 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 641267 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44906 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 44906 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 44906 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 44906 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 44906 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 44906 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596361 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 596361 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 596361 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 596361 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 596361 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.078709 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.595458 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 360794 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 473.291027 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 12676660 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 361148 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 35.101011 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4139080 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97568 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 97568 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94890 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 94890 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 12448715 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 12448715 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 12448715 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 12448715 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 397211 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 397211 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1557491 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 1954702 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 1954702 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 1954702 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6036826508 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 6036826508 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80166814063 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 80166814063 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129072992 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 129072992 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53027415 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 53027415 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 86203640571 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 86203640571 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 86203640571 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 86203640571 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706846 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 8706846 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696571 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 5696571 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111555 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 111555 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105474 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 105474 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 14403417 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 14403417 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 14403417 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 14403417 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045621 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.045621 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273409 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.273409 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125382 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125382 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9228.068349 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9228.068349 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5010.148810 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5010.148810 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 44100.656044 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 44100.656044 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 29197 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 19426 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 3289 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.877166 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 324862 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|