1416 lines
27 KiB
INI
1416 lines
27 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
eventq_index=0
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|
full_system=true
|
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sim_quantum=0
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
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|
|
|
[system]
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type=LinuxAlphaSystem
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children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
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boot_cpu_frequency=500
|
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/scratch/nilay/GEM5/system/binaries/console
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eventq_index=0
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
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load_addr_mask=1099511627775
|
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mem_mode=timing
|
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mem_ranges=0:134217727
|
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memories=system.physmem
|
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num_work_ids=16
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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system_type=34
|
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
|
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clk_domain=system.clk_domain
|
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delay=50000
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eventq_index=0
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ranges=8796093022208:18446744073709551615
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req_size=16
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resp_size=16
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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eventq_index=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=DerivO3CPU
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children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
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LFSTSize=1024
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LQEntries=32
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LSQCheckLoads=true
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LSQDepCheckShift=4
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SQEntries=32
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SSITSize=1024
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activity=0
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backComSize=5
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branchPred=system.cpu.branchPred
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cachePorts=200
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checker=Null
|
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clk_domain=system.cpu_clk_domain
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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commitToRenameDelay=1
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commitWidth=8
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cpu_id=0
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decodeToFetchDelay=1
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decodeToRenameDelay=1
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decodeWidth=8
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dispatchWidth=8
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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iewToCommitDelay=1
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iewToDecodeDelay=1
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iewToFetchDelay=1
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iewToRenameDelay=1
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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issueToExecuteDelay=1
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issueWidth=8
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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needsTSO=false
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numIQEntries=64
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numPhysCCRegs=0
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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profile=0
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progress_interval=0
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renameToDecodeDelay=1
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renameToFetchDelay=1
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renameToIEWDelay=2
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renameToROBDelay=1
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renameWidth=8
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simpoint_start_insts=
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smtCommitPolicy=RoundRobin
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smtFetchPolicy=SingleThread
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smtIQPolicy=Partitioned
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smtIQThreshold=100
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smtLSQPolicy=Partitioned
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smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.branchPred]
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type=BranchPredictor
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BTBEntries=4096
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BTBTagSize=16
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RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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eventq_index=0
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globalCtrBits=2
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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predType=tournament
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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size=32768
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[system.cpu.dtb]
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type=AlphaTLB
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eventq_index=0
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size=64
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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eventq_index=0
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList
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count=6
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eventq_index=0
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opList=system.cpu.fuPool.FUList0.opList
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[system.cpu.fuPool.FUList0.opList]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=IntAlu
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opLat=1
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[system.cpu.fuPool.FUList1]
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type=FUDesc
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children=opList0 opList1
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count=2
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eventq_index=0
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=19
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opClass=IntDiv
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opLat=20
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[system.cpu.fuPool.FUList2]
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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eventq_index=0
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatAdd
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opLat=2
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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eventq_index=0
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issueLat=1
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opClass=FloatCvt
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opLat=2
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[system.cpu.fuPool.FUList3]
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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eventq_index=0
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu.fuPool.FUList3.opList0]
|
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type=OpDesc
|
|
eventq_index=0
|
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issueLat=1
|
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opClass=FloatMult
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opLat=4
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|
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[system.cpu.fuPool.FUList3.opList1]
|
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type=OpDesc
|
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eventq_index=0
|
|
issueLat=12
|
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opClass=FloatDiv
|
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opLat=12
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[system.cpu.fuPool.FUList3.opList2]
|
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type=OpDesc
|
|
eventq_index=0
|
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issueLat=24
|
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opClass=FloatSqrt
|
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opLat=24
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|
|
|
[system.cpu.fuPool.FUList4]
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type=FUDesc
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children=opList
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count=0
|
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eventq_index=0
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|
opList=system.cpu.fuPool.FUList4.opList
|
|
|
|
[system.cpu.fuPool.FUList4.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
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issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5]
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type=FUDesc
|
|
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
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count=4
|
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eventq_index=0
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|
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
|
|
|
[system.cpu.fuPool.FUList5.opList00]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList01]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAddAcc
|
|
opLat=1
|
|
|
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[system.cpu.fuPool.FUList5.opList02]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList03]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList04]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList05]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList06]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList07]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList08]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShift
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList09]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShiftAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList10]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList11]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList12]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList13]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList14]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList15]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatDiv
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList16]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList17]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList18]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList19]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList6]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList6.opList
|
|
|
|
[system.cpu.fuPool.FUList6.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
|
|
|
[system.cpu.fuPool.FUList7.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList8]
|
|
type=FUDesc
|
|
children=opList
|
|
count=1
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList8.opList
|
|
|
|
[system.cpu.fuPool.FUList8.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=3
|
|
opClass=IprAccess
|
|
opLat=3
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=1
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
size=32768
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=1
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=2
|
|
size=32768
|
|
|
|
[system.cpu.interrupts]
|
|
type=AlphaInterrupts
|
|
eventq_index=0
|
|
|
|
[system.cpu.isa]
|
|
type=AlphaISA
|
|
eventq_index=0
|
|
|
|
[system.cpu.itb]
|
|
type=AlphaTLB
|
|
eventq_index=0
|
|
size=48
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=20
|
|
is_top_level=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
size=4194304
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=20
|
|
size=4194304
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentBus
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
eventq_index=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.disk0]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.disk0.image
|
|
|
|
[system.disk0.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.disk0.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.disk0.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
|
read_only=true
|
|
|
|
[system.disk2]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.disk2.image
|
|
|
|
[system.disk2.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.disk2.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.disk2.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
|
read_only=true
|
|
|
|
[system.intrctrl]
|
|
type=IntrControl
|
|
eventq_index=0
|
|
sys=system
|
|
|
|
[system.iobus]
|
|
type=NoncoherentBus
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
use_default_range=true
|
|
width=8
|
|
default=system.tsunami.pciconfig.pio
|
|
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
|
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
|
|
|
[system.iocache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:134217727
|
|
assoc=8
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
forward_snoops=false
|
|
hit_latency=50
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=50
|
|
size=1024
|
|
system=system
|
|
tags=system.iocache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.iobus.master[29]
|
|
mem_side=system.membus.slave[2]
|
|
|
|
[system.iocache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
hit_latency=50
|
|
size=1024
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
children=badaddr_responder
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
default=system.membus.badaddr_responder.pio
|
|
master=system.bridge.slave system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|
|
|
[system.membus.badaddr_responder]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=0
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=true
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.membus.default
|
|
|
|
[system.physmem]
|
|
type=SimpleDRAM
|
|
activation_limit=4
|
|
addr_mapping=RaBaChCo
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
devices_per_rank=8
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
mem_sched_policy=frfcfs
|
|
null=false
|
|
page_policy=open
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCL=13750
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=300000
|
|
tRP=13750
|
|
tRRD=6250
|
|
tWTR=7500
|
|
tXAW=40000
|
|
write_buffer_size=32
|
|
write_high_thresh_perc=70
|
|
write_low_thresh_perc=0
|
|
port=system.membus.master[1]
|
|
|
|
[system.simple_disk]
|
|
type=SimpleDisk
|
|
children=disk
|
|
disk=system.simple_disk.disk
|
|
eventq_index=0
|
|
system=system
|
|
|
|
[system.simple_disk.disk]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
|
read_only=true
|
|
|
|
[system.terminal]
|
|
type=Terminal
|
|
eventq_index=0
|
|
intr_control=system.intrctrl
|
|
number=0
|
|
output=true
|
|
port=3456
|
|
|
|
[system.tsunami]
|
|
type=Tsunami
|
|
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
|
eventq_index=0
|
|
intrctrl=system.intrctrl
|
|
system=system
|
|
|
|
[system.tsunami.backdoor]
|
|
type=AlphaBackdoor
|
|
clk_domain=system.clk_domain
|
|
cpu=system.cpu
|
|
disk=system.simple_disk
|
|
eventq_index=0
|
|
pio_addr=8804682956800
|
|
pio_latency=100000
|
|
platform=system.tsunami
|
|
system=system
|
|
terminal=system.terminal
|
|
pio=system.iobus.master[24]
|
|
|
|
[system.tsunami.cchip]
|
|
type=TsunamiCChip
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=8803072344064
|
|
pio_latency=100000
|
|
system=system
|
|
tsunami=system.tsunami
|
|
pio=system.iobus.master[0]
|
|
|
|
[system.tsunami.ethernet]
|
|
type=NSGigE
|
|
BAR0=1
|
|
BAR0LegacyIO=false
|
|
BAR0Size=256
|
|
BAR1=0
|
|
BAR1LegacyIO=false
|
|
BAR1Size=4096
|
|
BAR2=0
|
|
BAR2LegacyIO=false
|
|
BAR2Size=0
|
|
BAR3=0
|
|
BAR3LegacyIO=false
|
|
BAR3Size=0
|
|
BAR4=0
|
|
BAR4LegacyIO=false
|
|
BAR4Size=0
|
|
BAR5=0
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=2
|
|
Command=0
|
|
DeviceID=34
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=30
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=52
|
|
MinimumGrant=176
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=0
|
|
Revision=0
|
|
Status=656
|
|
SubClassCode=0
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=4107
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
dma_data_free=false
|
|
dma_desc_free=false
|
|
dma_no_allocate=true
|
|
dma_read_delay=0
|
|
dma_read_factor=0
|
|
dma_write_delay=0
|
|
dma_write_factor=0
|
|
eventq_index=0
|
|
hardware_address=00:90:00:00:00:01
|
|
intr_delay=10000000
|
|
pci_bus=0
|
|
pci_dev=1
|
|
pci_func=0
|
|
pio_latency=30000
|
|
platform=system.tsunami
|
|
rss=false
|
|
rx_delay=1000000
|
|
rx_fifo_size=524288
|
|
rx_filter=true
|
|
rx_thread=false
|
|
system=system
|
|
tx_delay=1000000
|
|
tx_fifo_size=524288
|
|
tx_thread=false
|
|
config=system.iobus.master[28]
|
|
dma=system.iobus.slave[2]
|
|
pio=system.iobus.master[27]
|
|
|
|
[system.tsunami.fake_OROM]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8796093677568
|
|
pio_latency=100000
|
|
pio_size=393216
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[8]
|
|
|
|
[system.tsunami.fake_ata0]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848432
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[19]
|
|
|
|
[system.tsunami.fake_ata1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848304
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[20]
|
|
|
|
[system.tsunami.fake_pnp_addr]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848569
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[9]
|
|
|
|
[system.tsunami.fake_pnp_read0]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848451
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[11]
|
|
|
|
[system.tsunami.fake_pnp_read1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848515
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[12]
|
|
|
|
[system.tsunami.fake_pnp_read2]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848579
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[13]
|
|
|
|
[system.tsunami.fake_pnp_read3]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848643
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[14]
|
|
|
|
[system.tsunami.fake_pnp_read4]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848707
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[15]
|
|
|
|
[system.tsunami.fake_pnp_read5]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848771
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[16]
|
|
|
|
[system.tsunami.fake_pnp_read6]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848835
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[17]
|
|
|
|
[system.tsunami.fake_pnp_read7]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848899
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[18]
|
|
|
|
[system.tsunami.fake_pnp_write]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615850617
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[10]
|
|
|
|
[system.tsunami.fake_ppc]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848891
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[7]
|
|
|
|
[system.tsunami.fake_sm_chip]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848816
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[2]
|
|
|
|
[system.tsunami.fake_uart1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848696
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[3]
|
|
|
|
[system.tsunami.fake_uart2]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848936
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[4]
|
|
|
|
[system.tsunami.fake_uart3]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848680
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[5]
|
|
|
|
[system.tsunami.fake_uart4]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=8804615848944
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[6]
|
|
|
|
[system.tsunami.fb]
|
|
type=BadDevice
|
|
clk_domain=system.clk_domain
|
|
devicename=FrameBuffer
|
|
eventq_index=0
|
|
pio_addr=8804615848912
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[21]
|
|
|
|
[system.tsunami.ide]
|
|
type=IdeController
|
|
BAR0=1
|
|
BAR0LegacyIO=false
|
|
BAR0Size=8
|
|
BAR1=1
|
|
BAR1LegacyIO=false
|
|
BAR1Size=4
|
|
BAR2=1
|
|
BAR2LegacyIO=false
|
|
BAR2Size=8
|
|
BAR3=1
|
|
BAR3LegacyIO=false
|
|
BAR3Size=4
|
|
BAR4=1
|
|
BAR4LegacyIO=false
|
|
BAR4Size=16
|
|
BAR5=1
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=1
|
|
Command=0
|
|
DeviceID=28945
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=31
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=0
|
|
MinimumGrant=0
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=133
|
|
Revision=0
|
|
Status=640
|
|
SubClassCode=1
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=32902
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
ctrl_offset=0
|
|
disks=system.disk0 system.disk2
|
|
eventq_index=0
|
|
io_shift=0
|
|
pci_bus=0
|
|
pci_dev=0
|
|
pci_func=0
|
|
pio_latency=30000
|
|
platform=system.tsunami
|
|
system=system
|
|
config=system.iobus.master[26]
|
|
dma=system.iobus.slave[1]
|
|
pio=system.iobus.master[25]
|
|
|
|
[system.tsunami.io]
|
|
type=TsunamiIO
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
frequency=976562500
|
|
pio_addr=8804615847936
|
|
pio_latency=100000
|
|
system=system
|
|
time=Thu Jan 1 00:00:00 2009
|
|
tsunami=system.tsunami
|
|
year_is_bcd=false
|
|
pio=system.iobus.master[22]
|
|
|
|
[system.tsunami.pchip]
|
|
type=TsunamiPChip
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=8802535473152
|
|
pio_latency=100000
|
|
system=system
|
|
tsunami=system.tsunami
|
|
pio=system.iobus.master[1]
|
|
|
|
[system.tsunami.pciconfig]
|
|
type=PciConfigAll
|
|
bus=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=0
|
|
pio_latency=30000
|
|
platform=system.tsunami
|
|
size=16777216
|
|
system=system
|
|
pio=system.iobus.default
|
|
|
|
[system.tsunami.uart]
|
|
type=Uart8250
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=8804615848952
|
|
pio_latency=100000
|
|
platform=system.tsunami
|
|
system=system
|
|
terminal=system.terminal
|
|
pio=system.iobus.master[23]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|