fbc1feb39a
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
96 lines
1.9 KiB
INI
96 lines
1.9 KiB
INI
[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu membus monitor physmem
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.clk_domain]
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type=SrcClockDomain
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children=voltage_domain
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clock=1000
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voltage_domain=system.clk_domain.voltage_domain
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[system.clk_domain.voltage_domain]
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type=VoltageDomain
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voltage=1.000000
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[system.cpu]
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type=TrafficGen
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clk_domain=system.clk_domain
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config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
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elastic_req=false
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system=system
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port=system.monitor.slave
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[system.membus]
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type=NoncoherentBus
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clk_domain=system.clk_domain
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header_cycles=1
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use_default_range=false
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width=16
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master=system.physmem.port
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slave=system.monitor.master system.system_port
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[system.monitor]
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type=CommMonitor
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bandwidth_bins=20
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burst_length_bins=20
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clk_domain=system.clk_domain
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disable_addr_dists=true
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disable_bandwidth_hists=false
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disable_burst_length_hists=false
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disable_itt_dists=false
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disable_latency_hists=false
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disable_outstanding_hists=false
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disable_transaction_hists=false
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itt_bins=20
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itt_max_bin=100000
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latency_bins=20
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outstanding_bins=20
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read_addr_mask=18446744073709551615
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sample_period=1000000000
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trace_file=monitor.ptrc.gz
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transaction_bins=20
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write_addr_mask=18446744073709551615
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master=system.membus.slave[0]
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slave=system.cpu.port
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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port=system.membus.master[0]
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